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nonvolatile memory, quad 64-position digital potentiometer ad5233 rev. a in fo rmation furn ished by an alog d e v i c e s is believed to be accurate and reliable. how e ver, n o resp on sibili ty is assume d b y a n alog de vices fo r its use, nor for an y i n fri n geme nt s of p a t e nt s or ot h e r ri ght s o f th ird parties th at may result fro m its use . s p ecificatio n s subj ec t to ch an g e witho u t n o tice. no licen s e is g r an te d by implicati o n or ot herwi s e u n der a n y p a t e nt or p a t e nt ri ghts of analog de v i ces. trademarks an d registered tra d ema r ks are the prop erty o f their respective ow ners. one technolog y way, p.o . box 9106, norwood, ma 02062-9106, u.s.a. t e l: 781. 329. 4 700 www.analog.com fax: 781. 326. 87 03 ? 2004 analog de vices, i n c. al l r i ght s r e ser v ed . features nonvolatile me mory stores wiper setting 4-channel independent programmable 64-position resolution power-on refreshed with eem em settings eemem restore time: 14 0 s t y p full monotonic operation 10 k?, 50 k?, a n d 100 k? ter m inal resistanc e permanent me mory write protection wiper setting r eadback predefine d line ar increment/decrement instr u ctions predefine d 6 db/step log taper increment/decrement instructions spi?-compatibl e serial interfac e with readbac k function 3 v to 5 v s i ngle supply o r 2. 5 v dua l supply 11 bytes extra nonvolatile me mory for user- d efined data 100-y ear t y pical dat a retenti o n, t a = 5 5 c applic ati o ns mechanical pot e ntiometer replacement instrumentation: gain, offset a d justment programmable voltage-to-cur rent conversion programmable filters, dela ys, time constants programmable power supply sensor calibration general description the ad5233 is a q u ad-c ha nn e l n o n v ol a t ile m e m o r y , 1 dig i t a l l y c o nt r o l l e d p o t e nt i o m e t e r 2 wi th 64- s t e p r e so l u tio n . th e de v i ce p e r f or ms t h e s a me el e c t r on i c a d j u st me n t f u nc t i on a s a m e ch a n ic a l p o ten t iom e ter w i t h en han c e d r e s o l u t i o n , s o lid st a t e r e liab ili t y , an d rem o t e co n t r o l l a b ili t y . th e ad5 233 has v e rs a t il e p r og ra mmin g usin g a n s p i-com p a t i b le s e r i al in t e r f ace f o r 16 m o des o f o p er a t io n a nd a d j u st m e n t i n cl u d i n g s c r a tch p ad p r og ra mmin g , m e m o r y st o r in g a nd r e st o r ing, in cr e m en t/ d e c r e m en t , 6 db / s t e p l o g ta pe r a d j u s t m e n t , w i pe r se t t i n g r e ad b a ck, an d e x t r a eemem fo r us er -def ine d i n fo r m a t io n such a s m e mor y d a t a f o r ot he r c o m p one n t s , l o o k - u p t a bl e s , or s y ste m i d e n ti f i ca ti o n inf o rm a t i o n . func ti on a l bl ock di a g r a m o1 addr decode ad5233 02794-a - 001 sdi serial interf a c e cs clk sdi sdo sdo pr wp rdy eemem control rdac1 register v dd 11 bytes user eemem digital 5 register digital output buffer o2 eemem5 rdac1 w1 b1 a1 v ss rdac2 register eemem2 eemem1 rdac3 register eemem3 rdac4 register eemem4 rdac2 w2 b2 a2 rdac3 w3 b3 a3 rdac4 w4 b4 a4 2 gnd fi g u r e 1 . i n t h e scra t c h p ad p r ogra mmin g m o de , a sp ecif ic set t in g can be p r og ra mm e d dir e c t l y t o th e rd a c 2 r e g i s t er , w h ich s e ts t h e r e sist a n c e b e twe e n t e r m ina l s w C a an d w C b . this s e t t ing can b e s t ore d i n to t h e e e m e m a n d i s t r ans f e r re d a u toma t i c a l l y to t h e r d a c r e g i st er d u r i n g sys t e m p o w e r - on. the eemem co n t en t c a n be r e st o r ed d y na mica ll y o r thr o ug h ext e r n al pr st r o b i n g , an d a wp f u nc t i on prote c t s e e m e m c o n t e n t s . t o s i m p l i f y t h e p r o g r a m m i n g , i n d e p e n d e n t o r s i m u l t a n eo us in cr e m en t o r d e cr e m en t co m m a n d s ca n b e used t o m o v e t h e r d a c w i p e r u p o r do wn, on e st ep a t a t i m e . f o r l o g a ri th m i c 6 d b s t e p c h a n g e s i n w i pe r se t t i n gs , th e l e ft o r r i g h t b i t sh if t comman d can b e us e d t o do ub le o r ha lv e t h e rd a c wi p e r s e t t ing. the ad5233 is a v a i la b l e in a t h in t sso p - 24 p a c k a g e . th e p a r t is gua r a n te e d t o o p era t e o v er t h e ext e nde d i n d u s t r i al t e m p er a - t u r e ra n g e o f ?40c t o +85c. 1 t h e t e r m s non v ola t il e memor y and ee me m are used in t e rchangeabl y . 2 t h e t e r m s d i gital pot e n t iome t e r and rd a c are used in t e rchangeabl y .
ad5233 rev. a | page 2 of 28 table of contents specifications ..................................................................................... 3 electrical characteristics10 k?, 50 k?, and 100 k? versions .......................................................................................... 3 timing characteristics ................................................................ 5 absolute maximum ratings ............................................................ 7 esd caution .................................................................................. 7 pin configuration and function descriptions ............................. 8 typical performance characteristics ............................................. 9 te s t c i rc u it s ................................................................................. 12 theory of operation ...................................................................... 14 scratchpad and eemem programming .................................. 14 basic operation .......................................................................... 14 eemem protection .................................................................... 15 digital input/output configuration ........................................ 15 serial data interface ................................................................... 15 daisy-chain operation ............................................................. 16 terminal voltage operation range .......................................... 16 power-up sequence ................................................................... 16 latched digital outputs ............................................................ 16 advanced control modes ......................................................... 18 rdac structure .......................................................................... 19 programming the variable resistor ......................................... 19 programming the potentiometer divider ............................... 20 programming examples ............................................................ 20 flash/eemem reliability .......................................................... 21 applications ..................................................................................... 22 bipolar operation from dual supplies .................................... 22 gain control compensation .................................................... 22 high voltage operation ............................................................. 22 dac .............................................................................................. 22 bipolar programmable gain amplifier ................................... 23 programmable low-pass filter ................................................ 23 programmable state-variable filter ......................................... 23 programmable oscillator .......................................................... 24 programmable voltage source with boosted output ............ 25 programmable current source ................................................ 25 programmable bidirectional current source ......................... 26 resistance scaling ...................................................................... 26 doubling the resolution ........................................................... 27 r e s i st a nc e to l e r anc e, d r i f t , a n d te mp e r atu re mi s m atc h considerations ............................................................................ 27 rdac circuit simulation model ............................................. 27 outline dimensions ....................................................................... 28 ordering guide .......................................................................... 28 revision history 7/04data sheet changed from rev. 0 to rev. a format updated................................................................... universal changes to features, general description, and block diagram .1 changes to specifications .................................................................3 replaced timing diagrams..............................................................6 changes to absolute maximum ratings ........................................7 changes to pin function descriptions...........................................8 replaced figure 11 ...........................................................................9 added test circuit (figure 36) ......................................................13 changes to theory of operation ..................................................14 changes to applications .................................................................22 updated outline dimensions........................................................28 changes to ordering guide ...........................................................28 3/02revision 0: initial version
ad5233 rev. a | page 3 of 28 specifications electrical characteristics10 k? , 50 k?, and 100 k? versions v dd = 3 v 10% or 5 v 10%, v ss = 0 v, v a = v dd , v b = 0 v, ?40c < t a < +85c, unless otherwise noted. table 1. parameter symbol conditions min typ 1 max unit dc characteristics, rheostat mode resistor differential nonlinearity 2 r-dnl r wb , v a = nc, monotonic ?0.5 0.1 +0.5 lsb resistor integral nonlinearity 2 r-inl r wb , v a = nc ?0.5 0.1 +0.5 lsb nominal resistor tolerance ?r ab /r ab d = 0x3f ?40 +20 % resistance temperature coefficient (?r wb /r wb )/?t 10 6 600 ppm/c wiper resistance r w i w = 100 a, code = half scale 15 100 ? dc characteristics, potentiometer divider mode resolution n 6 bits differential nonlinearity 3 dnl monotonic ?0.5 +0.1 +0.5 lsb integral nonlinearity 3 inl ?0.5 +0.1 +0.5 lsb voltage divider temperature coefficient (?v w /v w )/?t 10 6 code = half scale 15 ppm/c full-scale error v wfse code = full scale ?1.5 0 % fs zero-scale error v wzse code = zero scale 0 1.5 % fs resistor terminals terminal voltage range 4 v a, b, w v ss v dd v capacitance 5 a, b c a, b f = 1 mhz, measured to gnd, code = half scale 35 pf capacitance 5 w c w f = 1 mhz, measured to gnd, code = half scale 35 pf common-mode leakage current 5 , 6 i cm v w = v dd /2 0.015 1 a digital inputs and outputs input logic high v ih with respect to gnd, v dd = 5 v 2.4 v input logic low v il with respect to gnd, v dd = 5 v 0.8 v input logic high v ih with respect to gnd, v dd = 3 v 2.1 v input logic low v il with respect to gnd, v dd = 3 v 0.6 v input logic high v ih with respect to gnd, v dd = +2.5 v, v ss = ?2.5 v 2.0 v input logic low v il with respect to gnd, v dd = +2.5 v, v ss = ?2.5 v 0.5 v output logic high (sdo, rdy) v oh r pull-up = 2.2 k? to 5 v (see figure 25) 4.9 v output logic low v ol i ol = 1.6 ma, v logic = 5 v (see figure 25) 0.4 v input current i il v in = 0 v or v dd 2.5 a input capacitance 5 c il 4 pf output current 5 i o1 , i o2 v dd = 5 v, v ss = 0 v, t a = 25c, sourcing only 50 ma v dd = 2.5 v, v ss = 0 v, t a = 25c, sourcing only 7 ma power supplies single-supply power range v dd v ss = 0 v 2.7 5.5 v dual-supply power range v dd /v ss 2.25 2.75 v positive supply current i dd v ih = v dd or v il = gnd 3.5 10 a negative supply current i ss v ih = v dd or v il = gnd, v dd = +2.5 v, v ss = ?2.5 v 0.55 10 a
ad5233 rev. a | page 4 of 28 parameter symbol conditions min typ 1 max unit eemem store mode current i dd (store) v ih = v dd or v il = gnd, v ss = 0, i ss 0 40 ma i ss (store) v dd = +2.5 v, v ss = ?2.5 v ?40 ma eemem restore mode current 7 i dd (restore) v ih = v dd or v il = gnd, v ss = gnd, i ss 0 0.3 3 9 ma i ss (restore) v dd = +2.5 v, v ss = ?2.5 v ?0.3 ?3 ?9 ma power dissipation 8 p diss v ih = v dd or v il = gnd 0.018 0.05 mw power supply sensitivity 5 p ss ?v dd = 5 v 10% 0.002 0.01 %/% dynamic characteristics 5 , 9 bandwidth bw ?3 db, r ab = 10 k?/50 k?/ 100 k? 630/135/66 khz total harmonic distortion thd w v a = 1 v rms, v b = 0 v, f = 1 khz, r ab = 10 k? 0.04 % v a = 1 v rms, v b = 0 v, f = 1 khz, r ab = 50 k?, 100 k? 0.015 % v w settling time t s v a = v dd , v b = 0 v, v w = 0.50% error band, code 0x000 to 0x200 for r ab = 10 k?/50 k?/100 k? 0.6/2.2/3.8 s resistor noise voltage e n_wb r wb = 5 k?, f = 1 khz 9 nv/ hz crosstalk (c w1 /c w2 ) c t v a = v dd , v b = 0 v, measure v w with adjacent rdac making full-scale code change ?1 nv-s analog crosstalk (c w1 /c w2 ) c ta v dd = v a1 = +2.5 v, v ss = v b1 = ?2.5 v, measure v w1 with v w2 = 5 v p-p @ f = 10 khz, code 1 = 0x20, code 2 = 0x3f, r ab = 10 k?/50 k?/100 k? ?86/?73/ ?68 db 1 typicals represent average readings at 25c and v dd = 5 v. 2 resistor position nonlinearity error r-inl is the deviation fr om an ideal value measured between the maximum resistance and th e minimum resistance wiper positions. r-dnl measures the relative step change from ideal between successive tap positions. i w > 50 a @ v dd = 2.7 v for the r ab = 10 k? version, i w > 50 a for the r ab = 50 k? and i w > 25 a for the r ab = 100 k? version (see ). figure 25 3 inl and dnl are measured at v w with the rdac configured as a potentiometer divider similar to a voltage output adc. v a = v dd and v b = v ss . dnl specification limits of ?1 lsb minimum are guaranteed monotonic operating conditions (see f ). igure 26 4 resistor terminals a, b, and w have no limitations on polari ty with respect to each other. dual-supply operation enables groun d-referenced bipolar signal adjustment. 5 guaranteed by design and not subject to production test. 6 common-mode leakage current is a measur e of the dc leakage from terminals b and w to a common-mode bias level of v dd /2. 7 eemem restore mode current is not continuous. current consumed while eemem locations are read and transferred to the rdac regi ster (see ). to minimize power dissipation, a nop instruction should be issued immediately after instruction 1 (0x1). figure 22 8 p diss is calculated from (i dd v dd ) + (i ss v ss ). 9 all dynamic characteristics use v dd = +2.5 v and v ss = ?2.5 v.
ad5233 rev. a | page 5 of 28 timing characteristics v dd = 3 v to 5.5 v, v ss = 0 v, and ?40c < t a < +85c, unless otherwise noted. table 2. parameter symbol conditions min typ 1 max unit interface timing characteristics 2 , 3 clock cycle time (t cyc ) t 1 20 ns cs setup time t 2 10 ns clk shutdown time to cs rise t 3 1 t cyc input clock pulse width t 4 , t 5 clock level high or low 10 ns data setup time t 6 from positive clk transition 5 ns data hold time t 7 from positive clk transition 5 ns cs to sdo-spi line acquire t 8 40 ns cs to sdo-spi line release t 9 50 ns clk to sdo propagation delay 4 t 10 r p = 2.2 k?, c l < 20 pf 50 ns clk to sdo data hold time t 11 r p = 2.2 k?, c l < 20 pf 0 ns cs high pulse width 5 t 12 10 ns cs high to cs high 5 t 13 4 t cyc rdy rise to cs fall t 14 0 ns cs rise to rdy fall time t 15 0.1 0.15 ms read/store to nonvolatile eemem 6 t 16 applies to instructions 0x 2, 0x3, and 0x9 25 ms cs rise to clock rise/fall setup t 17 10 ns preset pulse width (asynchronous) t prw not shown in timing diagram 50 ns preset response time to wiper setting t presp pr pulsed low to refresh wiper positions 70 s power-on eemem restore time t eemem1 r ab = 10 k? 140 s flash/ee memory reliability endurance 7 100 kcycles data retention 8 100 years 1 typicals represent average readings at 25c and v dd = 5 v. 2 guaranteed by design and not subject to production test. 3 see the timing diagrams ( and ) for the location of the measured va lues. all input control voltages are specif ied with t figure 2 figure 3 r = t f = 2.5 ns (10% to 90% of 3 v) and timed from a voltage level of 1.5 v. swit ching characteristics are measured using both v dd = 3 v and v dd = 5 v. 4 propagation delay depends on the value of v dd , r pull-up , and c l . 5 valid for commands that do not activate the rdy pin. 6 rdy pin low only for commands 2, 3, 8, 9, 10, and the pr hardware pulse: cmd_8 > 1 ms; cmd_9, 10 > 0. 12 ms; cmd_2, 3 > 20 ms. device operation at t a = ?40c and v dd < 3 v extends the save time to 35 ms. 7 endurance is qualified to 100,000 cycles pe r jedec standard 22, method a117, and measure d at ?40c, +25c, and +85c; typical endurance at 25c is 700,000 cycles. 8 retention lifetime equivalent at junction temperature (t j ) = 55c per jedec standard 22, metho d a117. retention lifetime based on an activation energy of 0.6 ev derates with junction temperature, as shown in in the section. fi gure 45 flash/eemem reliability
ad5233 r e v. a | pa ge 6 o f 2 8 rdy b15 ? msb b0? lsb sdo cpha = 1 b15 b0 b16* *note: extra bit that is not defined, but normally lsb of character previously transmitted. the cpol = 1 micro controller command aligns the incoming data to the positive edge of the clock. 02794-a - 002 clk cpol = 1 t 2 t 1 t 5 t 10 t 8 t 14 t 11 t 9 t 15 t 16 t 17 t 13 t 12 t 3 t 4 b15 ? msb b0? lsb sdi high or low high or low t 6 t 7 cs f i g u re 2. c p ha = 1 ti ming d i ag r a m rdy b15 ? msb b0? lsb sdo cpha = 1 b15 b0 b16* *note: extra bit that is not defined, but normally lsb of character previously transmitted. the cpol = 1 micro controller command aligns the incoming data to the positive edge of the clock. 02794-a - 003 clk cpol = 1 t 2 t 1 t 5 t 10 t 8 t 14 t 11 t 9 t 15 t 16 t 17 t 13 t 12 t 3 t 4 b15 ? msb b0? lsb sdi high or low high or low t 6 t 7 cs f i g u re 3. c p ha = 0 ti ming d i ag r a m
ad5233 r e v. a | pa ge 7 o f 2 8 absolute maximum ra tings t a = 2 5 c , u n l e ss ot he r w i s e not e d. table 3. p a r a m e t e r s r a t i n g s v dd to gnd C0.3 v, +7 v v ss to gnd +0.3 v, ?7 v v dd to v ss 7 v v a , v b , v w to gn d v ss ? 0.3 v, v dd + 0.3 v i a , i w , i b pulsed 1 20 ma c o n t i n u o u s 2 m a digital inputs and output vo ltage to gnd ?0.3 v, v dd + 0.3 v operating temperature range 2 ?40c to +85c maximum junction temperature (t j max) 150c storage temperature ?65c to +150c lead temperature, soldering vapor phase (60 s) 215c infrared (15 s) 220c t h ermal resista n ce junction-to- ambient ja 128c/w t h ermal resista n ce junction-to- case jc 28c/w package power dissip a tion ( t j max ? t a )/ ja 1 m a ximum t e r minal curren t is boun d e d b y the maximum c u r r en t hand l i ng of the s w it ches, maxi m um pow e r d i ss ip a t ion of the pack age , and maximum ap pl ied v o l t age acr o s s an y t w o of the a, b , and w t e r minal s a t a giv e n r e si st a n c e . 2 i n cl udes programming of non v ol a t il e memor y . s t r e s s es a b o v e t h os e lis t e d u n de r a b s o l u t e m a xi m u m r a t i n g s ma y c a us e p e r m a n en t dama ge t o t h e de vice . this is a s t r e s s ra t i n g onl y a nd f u n c t i o n al op era t io n o f t h e de v i ce a t t h es e o r a n y o t h e r con d i t io n s ab o v e t h o s e i n dica t e d in t h e op era t io nal s e c t io n o f t h is sp e c if ic a t io n is no t im plie d . e x p o sur e t o a b s o l u te max i m u m ra t i ng co ndi t i on s fo r ex ten d e d p e r i o d s ma y a f fe c t de vice r e l i ab i l i t y . esd c a ution esd (electrostatic discharge) sensitive device. ele c tros tatic charg e s as high as 4000 v readily accumulate on the human body and test eq uipment and can discharge wi thout detection. although this product features proprietary esd protection circu i try, permanent dama ge may occur on devices subjected to high energy electrostatic discharges. theref ore, prop er esd precautions a r e recommended to avoid perform a nce degradation or l o ss of functiona l ity.
ad5233 r e v. a | pa ge 8 o f 2 8 pin conf igura t ion and fu nction descriptions 1 clk sdi sdo v ss gnd a1 rd y v dd a4 w4 o1 w1 o2 b4 b1 a3 a2 w3 02794-a - 005 w2 b3 b2 top view (not to scale) 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 ad5233 cs pr wp f i gure 4. pin config ur ation ta ble 4. pi n f u nct i on d e s c ri pt i o ns pin no. mnemonic description 1 o1 nonvolatile digital output 1. a d dress o1 = 0x 4, data bit position d0; defaul ts to logic 1 initially. 2 clk serial input register clock pin. s h ifts in one bit a t a time on posit ive cloc k edges. 3 sdi serial data inpu t pin. shifts in one bit at a time on pos itive clo c k clk edges. msb loaded first. 4 sdo serial data output pin. serves readback and dais y-chain function s. commands 9 and 10 activate th e sdo output fo r the read back f u nction, delayed by 16 or 17 cl ock puls es, depending on the cloc k po larit y before and after the data-word (see figure 2, figure 3, and ta ble 7). in other commands, the sdo shifts out the previously load ed sdi bit pattern, delayed by 16 or 17 clock pul s es, depending on the cloc k po larit y (see figure 2 a n d figure 3). t h is previous l y shif ted-o ut sdi can be used for daisy- chaining multip le d evices. whenever sdo i s used, a pull-up resistor in the r a nge of 1 k? to 10 k? is needed. 5 gnd ground pin, logic ground refer e nce. 6 v ss negative supply. connect to 0 v for single-sup ply app l ication s . if v ss is used in dual supply, it must be able to sink 40 ma for 25 ms when storing d a ta to eeme m . 7 a1 terminal a of rdac1. 8 w1 wiper terminal of rdac1, a ddr es s (rdac1) = 0 x 0. 9 b1 terminal b of rdac1. 10 a2 terminal a of rdac2. 11 w2 wiper terminal of rdac2, a ddr es s (rdac2) = 0 x 1. 12 b2 terminal b of rdac2. 13 b3 terminal b of rdac3. 14 w3 wiper terminal of rdac3, a ddr es s (rdac3) = 0 x 2. 15 a3 terminal a of rdac3. 16 b4 terminal b of rdac4. 17 w4 wiper terminal of rdac4, a ddr es s (rdac4) = 0 x 3. 18 a4 terminal a of rdac4. 1 9 v dd positive power s u pply pin. 20 wp optiona l write protect pin. when active lo w, wp p r events any cha n ges to the present contents, except pr strobe and instructions 1 and 8, and refreshes the rdac re gister from eemem. execute a nop instruction before returning to wp high. tie wp to v dd , if not used. 21 pr optional hardware override preset pin. refreshes the sc ratchpad register with current contents of the eem em register. factory d e fault load s mid scale 32 10 until eemem is load ed with a new value by the user. pr is activated at the logic high transition. tie pr to v dd , if not used. 22 cs serial register c h ip select active low. serial reg i ster operation takes place whe n cs returns to logic high. 2 3 r d y ready. active-high open-drain output. i d entifies co mpletion of instructions 2, 3, 8, 9, 10, and pr . 24 o2 nonvolati l e digital output 2. a d dress (o2) = 0x4, data bit positio n d1; defa ults to logic 1 initially.
ad5233 r e v. a | pa ge 9 o f 2 8 typical perf orm ance cha r acte ristics code (decimal) inl e rror (ls b ) 0.20 01 6 3 2 6 4 0.10 0 ? 0.10 ? 0.20 48 02794-a - 006 0.15 0.05 ? 0.05 ? 0.15 t a =+ 2 5 c t a = ?40 c t a =+ 8 5 c f i gure 5. inl vs. code , t a = ?4 0 c, + 25 c, +8 5 c o v e r la y , r ab = 10 k? 02794-a - 007 code (decimal) dnl e rror (ls b ) 0.20 0 16 32 64 0.10 ?0.10 ?0.20 48 0.15 0.05 0 ?0.05 ?0.15 t a =+ 2 5 c t a =? 4 0 c t a =+ 8 5 c f i gure 6. dnl vs. c o de , t a = ?4 0c, + 2 5c, +8 5c o v e r l a y , r ab = 10 k? 02794-a - 008 code (decimal) r-inl (ls b ) 0.20 01 6 3 2 6 4 0.10 ?0.10 ?0.20 48 0.15 0.05 0 ?0.05 ?0.15 v dd = 5v, v ss = 0v t a =+ 2 5 c t a =? 4 0 c t a =+ 8 5 c f i gure 7. r-inl vs. code , t a = ?4 0c, + 2 5c, +8 5c o v e r l a y , r ab = 10 k? code (decimal) 0.20 01 63 2 6 4 0.10 ? 0.10 ? 0.20 48 0.15 0.05 0 ? 0.05 ? 0.15 02794-a - 009 r-dnl (ls b ) v dd = 5v, v ss = 0v t a =+ 2 5 c t a =? 4 0 c t a =+ 8 5 c f i gure 8. r-dnl vs. c o de , t a = ?4 0c , + 2 5 c, + 8 5c o v er la y , r ab = 10 k? 02794-a - 010 code (decimal) 3000 0 16 32 64 2000 1000 0 48 2500 1500 500 rheostat mode te mp co (ppm/c) v dd = 5v, v ss = 0v t a = ? 40 c to +85c fi g u r e 9 . ( ? r wb /r wb )/?t 10 6 02794-a - 011 code (decimal) 300 01 6 3 2 6 4 100 0 48 200 p o te ntiome te r mode te mp co (ppm/ c) v dd = 5.5v, v ss = 0v t a = ? 40c to +85c v a = 2v v b = 0v f i g u re 10. (?v w /v w ) /?t 10 6 vs. c o d e , r ab = 10 k?
ad5233 rev. a | page 10 of 28 02794-a - 012 code (decimal) 80 0 16 32 64 40 0 48 60 20 r w ( ? ) v dd = 2.7v, v ss = 0v t a = 25c f i gure 11. wiper o n r e sistance v s . co de 02794-a - 013 temperature (c) 4 ?40 ? 20 0 2 04 06 0 1 0 0 3 ?1 80 1 0 2 curre nt ( a) i dd @ v dd /v ss = 5v/0v i ss @ v dd /v ss = 5v/0v i dd @ v dd /v ss = 2.7v/0v i ss @ v dd /v ss = 2.7v/0v f i g u re 12. i dd vs . t e m p er a t ur e , r ab = 1 0 k? midscale 02794-a - 014 clock frequency (mhz) 0.30 024 68 1 0 1 2 0.25 0.05 0 0.15 0.10 0.20 i dd (ma) zero scale full scale v dd = 5v v ss = 5v f i g u re 13. i dd vs . clo c k f r e q ue nc y , r ab = 1 0 k ? frequency (hz) gain ( d b) 3.0 1k 1m ? 6.0 ?12.0 ? 3.0 ? 9.0 0 10k 100k v dd @ v ss = 2.5v v a /1v ms d = midscale f ?3db = 66khz f ? 3db = 600khz, r ab = 10k ? f ? 3db = 132khz, r ab = 50k ? 02794-a - 015 f i gure 14. ? 3 db bandwidth vs. resistanc e ( f i gure 31) frequency (hz) thd + nois e (%) 0.05 10 100k 0.02 0 0.03 0.01 0.04 100 1k 10k r ab = 10k ? v dd /v ss = 2.5v v a = 1v ms 50k ? 100k ? 02794-a - 016 f i gure 15. t o t a l h a rm oni c d i s t o r ti on v s . f r equenc y 02794-a - 017 frequency (hz) amp l itude (db) 0 100 10m ?30 ?4 2 ?24 ?36 ?12 1k 10k 100k ?6 ?18 1m 0x01 0x02 0x04 0x08 0x10 code 0x20 f i gure 16. g a in vs. f r equ e nc y vs. c o d e , r ab = 1 0 ? ( f i g u re 31)
ad5233 rev. a | page 11 of 28 02794-a - 018 frequency (hz) amp l itude (db) 0 100 1m ?30 ?42 ?24 ?36 ?12 1k 10k 100k ?6 ?18 code 0x20 0x10 0x08 0x04 0x02 0x01 f i gure 17. g a in vs. f r equ e nc y vs. c o d e , r ab = 50 k ? ( f i gur e 31 ) 02794-a - 019 frequency (hz) amp l itude (db) 0 100 1m ?30 ?42 ?24 ?36 ?1 2 1k 10k 100k ?6 ?1 8 code 0x20 0x10 0x08 0x04 0x02 0x01 f i gure 18. g a in vs. f r equ e nc y vs. c o d e , r ab = 10 0 k? ( f i g u r e 31 ) 02794-a - 020 frequency (hz) p s rr (db) 80 0.1k 10m 1m 30 0 10 40 20 60 1k 10k 100k 70 50 v dd = 5v 100mv ac v ss = 0v, v a = 5v, v b = 0v measured at v w with code = 0x200 r ab = 100k ? r ab = 50k ? r ab = 10k ? fi g u r e 1 9 . p s r r v s . fr e q u e n c y 02794-a - 021 midscale expected value 100 s/div v dd = 5v v a = 2.25v v b = 0v v a v w 0.5v/ div f i g u re 20. p o wer - o n r e s e t , v a = 2.2 5 v , v b = 0 v , code = 10 10 1 0 02794-a - 022 time ( s) 2.60 2.58 2.56 0 5 100 250 350 450 200 150 300 400 511 2.54 2.52 2.42 2.40 2.46 2.44 2.50 2.48 v out (v ) v dd = v a = 5v v ss = v b = 0v code = 0x20 to 0x1f f i g u re 21. m i ds c a l e gli t ch e n er g y , cod e 0x 20 to 0x 1f 02794-a - 023 clk sdi i dd 20ma/ div 4ms/div 5v/div 5v/div 5v/div cs f i g u re 22. i dd vs . t i m e whe n sto r i n g d a ta to eemem
ad5233 rev. a | page 12 of 28 clk sdi i dd * 2ma/div 02794-a - 024 *supply current returns to minimum power consumption, if instruction 0 (nop) is executed immediately after instruction 1 (read eemem). 4ms/div 5v/div 5v/div 5v/div cs f i g u re 23. i dd vs . t i m e whe n re a d i n g da t a fr om eemem 1 0.01 0.1 code (decimal) 02794-a - 025 the o re tical (i wb _ m a x ?m a) 0 8 16 24 32 40 48 56 64 10 100 r ab = 10k ? r ab = 100k ? r ab = 50k ? v a = v b = open t a = 25c f i g u re 24. i max vs . co de test circui t s f i gur e 25 t o f i gur e 35 def i n e t h e t e st condi t i ons us e d in t h e sp e c if ica t ion s . a w b nc i w dut v ms nc = no connect 02794-a - 026 f i gur e 2 5 . resi st or p o si tio n no nl inea r i t y er r o r (r heo s ta t o p er a t ion; r - inl, r - dnl) 02794-a - 027 a w b dut v ms v+ v+ = v dd 1lsb = v+/2 n f i gure 26. p o tenti o meter d i v i d e r n o n l ine a r i t y e r r o r (inl, dnl) 02794-a - 028 a w b dut i w v ms1 v ms2 v w r w = [v ms1 ? v ms2 ]/i w f i gur e 2 7 . wi p e r resi sta n c e a w b v ms v+ = v dd 10% psrr (db) = 20 log 02794-a - 029 v a v dd pss (%/%) = ? v ms % ? v dd % ? v ms ? v dd () v+ f i g u re 28. p o wer s u p p ly s e ns it iv it y ( p ss, psr r ) offset bias offset gnd a dut b 02794-a - 030 w 5v v in v out op279 f i g u re 29. inve r t ing g a i n 02794-a - 031 offset bias offset gnd ab dut w 5v v in v out op279 f i gure 30. nonin v e r ting g a in
ad5233 rev. a | page 13 of 28 offset gn d a b dut w +15v v in v out op 42 ?15v 02794-a - 032 2. 5v fi g u r e 3 1 . g a i n v s . fr e q u e n c y 02794-a - 033 + dut code = 0x00 0.1v v bias r sw = 0.1v i sw i sw w b a = nc ? f i gu r e 3 2 . i n cr em en ta l on re si sta n c e dut v ss i cm w b v dd nc nc v cm gnd a nc = no connect 02794-a - 034 f i g u re 33. co m m o n -m ode l e ak ag e current v in a1 rdac1 w1 b1 nc nc = no connect v ss v dd a2 02794-a - 035 rdac2 w2 b2 v out c ta = 20 log v out v in () f i g u re 34. a n a l og cr os s t alk 02794-a - 036 200 ai ol 200 ai oh v oh (min) or v ol (max) t o output pin c l 50pf f i gure 35. l oad c i rcuit fo r me as ur ing v oh and v ol ( t h e dio d e br i d g e t e s t ci r c u i t is eq uiv a lent to th e a p pl ic ati o n ci r c u i t with r pu ll -u p of 2. 2 k ? .)
ad5233 rev. a | page 14 of 28 theory of operation the ad5233 digital potentiometer is designed to operate as a true variable resistor replacement device for analog signals that remain within the terminal voltage range of v ss < v term < v dd . the basic voltage range is limited to v dd ? v ss < 5.5 v. the digital potentiometer wiper position is determined by the rdac register contents. the rdac register acts as a scratchpad register, allowing as many value changes as necessary to place the potentiometer wiper in the correct position. the scratchpad register can be programmed with any position value using the standard spi serial interface mode by loading the complete representative data-word. once a desirable position is found, this value can be stored in an eemem register. thereafter, the wiper position is always restored to that position for subsequent power-up. the eemem data storing process takes approximately 25 ms; during this time, the shift register is locked, preventing any changes from taking place. the rdy pin pulses low to indicate the completion of this eemem storage. the following instructions facilitate the users programming needs (see table 7 for details): 0. do nothing. 1. restore eemem contents to rdac. 2. store rdac setting to eemem. 3. store rdac setting or user data to eemem. 4. decrement 6 db. 5. decrement all 6 db. 6. decrement one step. 7. decrement all one step. 8. reset eemem contents to rdacs. 9. read eemem contents from sdo. 10. read rdac wiper setting from sdo. 11. wr ite dat a to rdac. 12. increment 6 db. 13. increment all 6 db. 14. increment one step. 15. increment all one step. scratchpad and eemem programming the scratchpad rdac register directly controls the position of the digital potentiometer wiper. for example, when the scratch- pad register is loaded with all zeros, the wiper is connected to terminal b of the variable resistor. the scratchpad register is a standard logic register with no restriction on the number of changes allowed, but the eemem registers have a program erase/write cycle limitation (see the flash/eemem reliability section). basic operation the basic mode of setting the variable resistor wiper position (programming the scratchpad register) is accomplished by loading the serial data input register with instruction 11, addresses a1, a0, and the desired wiper position data. when the proper wiper position is determined, the user can load the serial data input register with instruction 2, which stores the wiper position data in the eemem register. after 25 ms, the wiper position is permanently stored in the nonvolatile memory location. table 5 provides a programming example listing the sequence of serial data input (sdi) words with the serial data output appearing at the sdo pin in hexadecimal format. table 5. set and store rdac data to eemem register sdi sdo action 0xb010 0xxxxx writes data 0x10 to the rdac1 register, wiper w1 moves to 1/4 full-scale position. 0x20xx 0xb010 stores rdac1 register content into the eemem1 register. at system power-on, the scratchpad register is automatically refreshed with the value previously stored in the eemem register. the factory-preset eemem value is midscale, but it can be changed by the user thereafter. during operation, the scratchpad (rdac) register can be refreshed with the eemem register data with instruction 1 or instruction 8. the rdac register can also be refreshed with the eemem register data under hardware control by pulsing the pr pin. the pr pulse first sets the wiper at midscale when brought to logic 0, and then, on the positive transition to logic high, it reloads the rdac wiper register with the contents of eemem. many additional advanced programming commands are available to simplify the variable resistor adjustment process (see table 7). for example, the wiper position can be changed one step at a time using the increment/decrement instruction or by 6 db with the shift left/right instruction. once an increment, decrement, or shift instruction has been loaded into the shift register, subsequent cs strobes can repeat this command. a serial data output sdo pin is available for daisy-chaining and for readout of the internal register contents.
ad5233 rev. a | page 15 of 28 eemem pro t ec tion the wr i t e p r o t e c t ( wp ) p i n dis a b l es a n y chan ges to t h e scra t c h p ad r e g i st er co n t en ts, ex cep t f o r th e eem em set t in g, w h ich c a n st i l l b e re store d u s ing i n st r u c t ion 1 , i n st r u c t ion 8 , a nd t h e pr p u ls e . ther efo r e , wp ca n be us e d t o p r o v ide a ha r d wa r e eem em p r o t ec tio n fea t ur e . t o disab l e wp , i t i s re c o m m e nd e d t o e x e c ute a no p i n st r u c t i o n b e f o re re tu r n i n g wp t o l o gi c h i gh . digit a l input/output c o nfigur a t ion all d i gi tal i n p u ts a r e es d p r o t e c t e d , h i g h in p u t i m pe da n c e tha t ca n b e dr i v en di r e c t ly f r o m m o st dig i t a l s o ur ces. a c t i ve a t lo g i c lo w , pr an d wp m u s t be tied t o v dd , i f th ey a r e n o t us ed . n o i n te r n a l pu l l - u p re s i s t or s are pre s e n t o n a n y d i g i t a l i n put pi ns . b e ca us e t h e de v i ce can b e det a ch e d f r o m t h e dr i v i n g s o ur ce o n ce i t is p r og ra mmed , adding p u l l -u p r e sis t ance o n t h e dig i ta l in p u t p i n s is a go o d w a y t o a v o i d fa ls e l y t r ig ger i n g t h e f l o a t i n g pi ns i n a noi s y e n v i ron m e n t . the s d o an d r d y p i n s a r e o p e n -drain dig i t a l o u t p uts t h a t n e e d p u l l -u p r e sis t o r s o n l y if thes e f u n c tion s a r e us e d . a r e sis t or val u e in t h e rang e o f 1 k? t o 10 k? is a p r o p er ch o i ce t h a t b a lan c es t h e p o w e r a nd s w i t chi n g s p e e d t r ade- o f f. serial d a t a interf a c e the ad5233 con t a i n s a 4 - wir e s p i co m p a t ib le dig i t a l in t e r f ace (s d i , s d o , cs , a nd cl k). i t us es a 16-b i t s e r i a l d a t a -w o r d lo aded ms b f i rst. th e f o r m a t o f th e s p i co m p a t i b le w o rd is s h own i n t a b l e 6. th e chi p - s e l e c t cs p i n m u s t be h e l d lo w un til th e co m p le t e da ta - w o r d i s loa d ed i n t o th e s d i p i n . w h en cs r e t u r n s hig h , t h e s e r i a l da t a - w or d is de co d e d ac co r d in g to t h e in st r u c t io n s in t a b l e 7. t h e comman d b i ts (c x) co n t r o l t h e o p er a t ion o f t h e dig i t a l p o te n t iom e ter . the address b i ts (ax ) det e r m i n e w h ich r e g i s t er is ac t i va t e d . th e da t a b i ts (d x) a r e t h e val u es t h a t a r e l o ade d i n t o t h e de co de d r e g i s t e r . t o p r og ra m rd a c 1 t o rd a c 4, o n l y th e 6 l s b da t a -b i t s a r e us ed . the ad5233 has a n in t e r n al coun t e r tha t co un ts a m u l t i p le o f 16 b i ts (a f r a m e) f o r p r o p er o p era t io n. f o r exa m p l e , ad5233 work s w i t h a 3 2 - b i t word, b u t i t c a n n ot wor k prop e r ly w i t h a 15-b i t o r 17-b i t w o r d . i n addi tion, ad5233 has a s u b t le f e a t ur e th a t , i f cs is p u ls ed wi t h o u t clk a nd s d i, the p a r t r e p e a t s t h e p r evio u s co mma nd (ex c ep t d u r i n g p o w e r - u p ). a s a r e s u l t , ca r e m u s t b e t a k e n to en s u r e t h a t n o exces s i v e n o is e exis ts in t h e clk o r cs lin e t h a t mig h t al t e r t h e ef fe c t i v e n u m b er -o f- b i ts p a t t er n. als o , t o p r ev en t da t a f r o m mis l o c k i n g (d ue t o n o is e , f o r exa m ple), t h e c o un t e r r e s e ts, if t h e co u n t is n o t a m u l t i p le o f fo u r w h en cs go es hig h . valid command coun ter command processor and address decode (for daisy chain only) seri al register c lk sdi 5v 02794-a - 037 r pull-up sdo gnd pr wp cs ad5233 f i gure 3 6 . e q ui v a l e nt di gi tal input- o u tput l o gi c the e q uiva len t s e r i a l da t a i n p u t a nd o u t p u t lo g i c is sh o w n i n f i gur e 36. t h e o p e n -d ra in o u t p u t s d o i s d i sa b l ed w h en ev e r chi p -s el e c t cs is in log i c hig h . the s p i in t e r f ace c a n b e us e d i n tw o s l a v e m o des: cp h a = 1, cpo l = 1 a nd cp h a = 0, cpo l = 0. cp h a and c p o l r e f e r t o th e co n t r o l b i ts tha t dic t a t e s p i t i m i ng i n t h e f o l l ow i n g m i c r o c on ve r t e r s a n d m i c r opro c e ss or s : aduc812/adu c 824, m68h c1 1, a n d m c 68 h c 16r1/916r1. es d p r o t e c t i on o f t h e dig i t a l i n p u ts is sh o w n i n f i gur e 37 a nd f i gur e 38. logic pins v dd gnd input 300 ? 02794-a - 038 f i gure 3 7 . e q ui v a l e nt esd di gi t a l inpu t p r ot ectio n v dd gnd input 300 ? 02794-a - 039 wp f i g u re 38. equiv a le nt wp input pr ot ec t i on
ad5233 rev. a | page 16 of 28 d a isy - chai n oper a t i o n the s e r i al da t a o u t p ut p i n (s d o ) s e r v es tw o p u r p os es. i t ca n b e used t o r e a d t h e co n t en t s o f th e w i pe r set t i n g a n d eemem va l u es usin g i n st r u c t io n s 10 a nd 9, r e sp e c t i ve ly . the r e ma in in g in s t r u c t io n s (0 to 8, 11 t o 15) a r e valid f o r da isy-c h a i nin g m u l t i p le de vice s in si m u l t an e o us o p era t io n s . d a isy - cha i nin g minimizes t h e n u m b er o f p o r t p i n s r e q u ir e d f r o m the co n t r o l l in g i c ( f igur e 39). th e s d o p i n con t a i n s a n op en-dra in n-c h fet t h a t r e q u ir es a p u l l - u p r e sist o r , if t h is f u n c t i on is us ed . a s sh o w n in f i gur e 39, us ers n e e d t o tie t h e s d o p i n o f o n e p a cka g e t o t h e s d i p i n o f t h e n e xt p a cka g e . u s ers mig h t ne e d t o i n cr e a s e t h e clo c k p e r i o d , b e ca us e t h e p u l l - u p r e sis t o r a nd th e ca p a c i ti v e lo adin g a t t h e s d o t o s d i in t e r f ace mig h t r e q u ir e a n a d d i t i o n a l t i m e d e l a y b e tw e e n s u bs e q uen t p a cka g es. w h en two ad5233s a r e da isy-c h a i n e d , 32 b i ts o f da ta ar e r e q u ir ed . th e f i rs t 16 b i ts g o t o u2 a nd t h e s e con d 16 b i ts go t o u1. the cs s h o u ld be k e p t lo w un til al l 32 b i ts a r e c l ock e d in t o th e i r r e specti v e s e ri al r e gi s t e r s. t h e cs is th en p u l l ed hig h t o co m p let e t h e op era t ion. sdi sdo clk r p 2k ? c sdi sdo clk u1 u2 ad5233 ad5233 02794-a - 040 cs cs +v f i g u re 39. d a is y- chai n co nf ig ur at i o n u s ing sdo terminal vol t a g e o p e r a t ion r a nge the ad5233 s p o si ti v e v dd and ne g a t i v e v ss po w e r s u p p l i e s def i ne t h e b o u nda r y co ndi t i on s fo r p r o p er 3-ter m ina l dig i t a l p o t e n t iom e t e r op era t ion. s u p ply sig n als p r es en t o n t e r m inals a, b , a n d w tha t ex ceed v dd or v ss a r e clam p e d b y t h e i n t e r n al fo r w a r d-b i as e d dio d es (s e e f i gu r e 40). v ss v dd a w b 02794-a - 041 f i g u re 40. m a x i mu m t e r m i n a l v o lt ag es s e t by v dd and v ss the g r o u nd p i n o f th e ad5233 de vice is us e d p r ima r il y as a dig i t a l g r o u nd r e fer e n c e, w h ich n e e d s to b e t i e d to t h e pc b s c o mm o n gr o u n d . th e di gi tal i n p u t c o n t r o l s i gnal s t o th e ad5233 m u st b e r e f e r e n c ed t o th e de vice g r o u nd p i n (gnd), a nd s a t i sf y t h e log i c le v e l def i n e d in t h e sp e c if ic a t io n s s e c t io n. an in t e r n al le v e l-s h if t c i r c ui t ens u r e s t h a t t h e c o mm on- m o d e v o l t a g e ra n g e o f t h e t h r e e t e r m i n als ext e n d s f r o m v ss to v dd , re g a rd l e ss of t h e d i g i t a l i n put l e vel. power-up sequence b e ca us e t h er e ar e dio d es t o limi t t h e v o l t a g e com p li an ce a t t e r m ina l s a, b , a nd w (f igur e 40), i t is im p o r t a n t t o p o w e r o n v dd /v ss f i r s t bef o r e a p p l yi n g a n y v o l t a g e t o t e r m i n als a, b , a n d w . o t h e r w is e , t h e dio d e is f o r w a r d-b i as e d s u c h tha t v dd /v ss ar e p o w e r e d uni n te n t io na l l y . f o r exa m ple, a p ply i n g 5 v acr o ss t e r m ina l s a and b p r io r t o v dd ca us es t h e v dd te r m i n a l to exhi b i t 4.3 v . i t i s n o t dest r u c t i v e t o t h e de vic e , b u t i t mi g h t a f fe c t t h e r e s t o f t h e us er s sys t e m . th e ide a l p o w e r - u p s e q u enc e is gnd , v dd , v ss , dig i t a l in p u ts, a nd v a /v b /v w . t h e ord e r of po w e ri n g v a , v b , v w , a n d dig i t a l in p u t s is n o t i m p o r t a n t as lo ng a s t h e y are p o w e re d af te r v dd /v ss . rega r d les s o f t h e p o w e r - u p s e q u en ce and t h e r a m p ra t e s o f th e po w e r s u p p l i e s , o n c e v dd /v ss a r e p o w e r e d , t h e p o w e r - o n p r es e t r e ma in s ef fe c t i v e , w h ich r e st o r es t h e eemem v a l u es t o t h e rd a c r e g i st ers. l a t c hed digit a l output s a p a i r of d i g i t a l output s , o 1 a n d o 2 , i s a v a i l a bl e on t h e a d 5 2 3 3 . th es e o u t p u t s p r o v ide a n o n v ol a t ile l o g i c 0 o r l o g i c 1 s e t t in g. o1 a nd o2 a r e st a n da r d cmos log i c o u t p u t s, sho w n in f i gur e 41. th es e o u t p uts a r e ide a l t o r e place t h e f u n c t i on s o f t e n p r o v ide d b y di p sw i t ch es. i n a ddi t i on, t h e y c a n b e us e d to dr i v e o t h e r s t anda r d cm os log i c-co n t r o l l ed p a r t s tha t n e e d an o c c a s i ona l s e t t i n g change. pi ns o 1 and o 2 d e f a u l t to l o g i c 1 , a nd t h e y c a n dr i v e u p to 50 m a o f lo ad a t 5 v/2 5 c. v dd gnd outputs o1 and o2 pins 02794-a - 042 f i gure 4 1 . l o gi c o u tputs o1 a n d o2
ad5233 rev. a | page 17 of 28 in table 6, command bits are c0 to c3, address bits are a3 to a0, data bits d0 to d5 are applicable to the rdac wiper register, and d0 to d7 are applicable to the eemem register. table 6. 16-bit serial data-word msb instruction byte lsb data byte rdac c3 c2 c1 c0 0 0 a1 a0 x x d5 d4 d3 d2 d1 d0 eemem c3 c2 c1 c0 a3 a2 a1 a0 d7 d6 d5 d4 d3 d2 d1 d0 command instruction codes are defined in table 7. table 7. instruction/operation truth table 1 , , 2 3 instruction byte 0 data byte 0 b16 b8 b7 b6 b5 b4 b3 b2 b1 b0 inst. no. c3 c2 c1 c0 a3 a2 a1 a0 d7 d6 d5 d4 d3 d2 d1 d0 operation 0 0 0 0 0 x x x x x x x x x x x x nop: do nothing. see table 14 for programming example. 1 0 0 0 1 0 0 a1 a0 x x x x x x x x restore eemem contents to rdac register. this command leaves the device in the read program power state. to return the part to the idle state, perform nop instruction 0. see table 14. 2 0 0 1 0 0 0 a1 a0 x x x x x x x x store wiper setting: store rdac (addr) setting to eemem. see table 13. 3 4 0 0 1 1 a3 a2 a1 a0 d7 d6 d5 d4 d3 d2 d1 d0 store contents of serial register data byte 0 (total 8 bits) to eemem (addr). see table 16. 4 5 0 1 0 0 0 0 a1 a0 x x x x x x x x decrement 6 db: right-shift contents of rdac register, stop at all 0s. 5 5 0 1 0 1 x x x x x x x x x x x x decrement all 6 db: right-shift contents of all rdac registers, stop at all 0s. 6 5 0 1 1 0 0 0 a1 a0 x x x x x x x x decrement content of rdac register by 1, stop at all 0s. 7 5 0 1 1 1 x x x x x x x x x x x x decrement contents of all rdac registers by 1, stop at all 0s. 8 1 0 0 0 x x x x x x x x x x x x reset: refresh all rdacs with their corresponding eemem previously stored values. 9 1 0 0 1 a3 a2 a1 a0 x x x x x x x x read content of eemem (addr) from sdo output in the next frame. see table 17. 10 1 0 1 0 0 0 a1 a0 x x x x x x x x read rdac wiper setting from sdo output in the next fr ame. see table 18. 11 1 0 1 1 0 0 a1 a0 x x d5 d4 d3 d2 d1 d0 write contents of serial register data byte 0 (total 6 bits) to rdac. see table 12. 12 5 1 1 0 0 0 0 a1 a0 x x x x x x x x increment 6 db: left-shift contents of rdac register, stop at all 1s. see table 15. 13 5 1 1 0 1 x x x x x x x x x x x x increment all 6 db: left-shift contents of rdac registers, stop at all 1s. 14 5 1 1 1 0 0 0 a1 a0 x x x x x x x x increment contents of rdac register by 1, stop at all 1s. see table 13. 15 5 1 1 1 1 x x x x x x x x x x x x increment contents of all rdac registers by 1, stop at all 1s. 1 the sdo output shifts out the last 16 bits of data clocked into the serial register for daisy-chain operation. exception: for any instruction following instruction 9 or 10, see details of these instructions for proper usage. 2 the rdac register is a volatile scratchpad register that is automatically refreshed at power-on from the corresponding nonvola tile eemem register. 3 execution of these operations takes place when the cs strobe returns to logic high. 4 instruction 3 writes one data byte (8 bits of data) to eemem. in the case of addresses 0, 1, 2, and 3, only the last 6 bits ar e valid for wiper position setting. 5 the increment, decrement, and shift instructions ignore the contents of the shift register data byte 0.
ad5233 rev. a | page 18 of 28 ad v a nce d c o ntrol m o des the ad5233 dig i tal p o t e n t iomet e r in c l udes a s e t o f us er p r og ra mmin g fe a t ur es t o addr e s s t h e wi de n u m b er o f a p plic a t ion s fo r t h es e uni v ers a l ad j u s t m e n t de vi ces. k e y p r og ra mmin g f e a t ur es in c l ude ? s c ra t c h p ad p r o g ra mmin g t o a n y d e sira b l e val u es ? n o n v ol a t i l e m e m o r y s t o r a g e o f t h e s c r a t c h p ad rd a c r e g i st er val u e in t h e ee mem r e g i s t er ? i n cr em en t a n d d e cr e m en t i n s t r u cti o n s f o r th e r d a c w i pe r re g i ste r ? l e f t and r i g h t b i t-shif t o f t h e r d a c wi p e r r e g i st er t o achi e v e 6 db l e vel ch ange s ? e l e v en ext r a b y tes o f us er -addr e s s a b l e n o n v ol a t i l e m e m o r y linear in cr em ent an d d e c r e m ent ins t r u cti o ns the in cr em en t a nd decr em en t in s t r u c t io n s (14, 15, 6, a n d 7) a r e u s e f u l for l i ne ar ste p - a dj u s t m e n t a p pl i c a t i o ns . t h e s e c o m m a nd s sim p lif y micr o c o n tr ol ler s o f t war e co din g b y al l o win g t h e co n t r o l l er to s e nd j u st a n i n cr em e n t o r de cr e m en t co m m an d to th e de v i ce . f o r a n i n cr em en t co m m a n d , e x ecu t i n g i n s t r u cti o n 14 w i t h th e p r o p e r a d d r e s s a u t o ma ticall y m o v e s th e wi pe r t o th e n e xt r e sis t a n c e s e g m en t p o si tion. i n str u c t io n 15 p e r f o r m s th e s a m e f u nc t i o n , e x c e pt t h a t t h e a d d r e s s d o e s no t ne e d to b e s p e c i f i e d. a l l r d a c s are ch ange d a t t h e s a m e t i me. logarithmi c t a p e r mo de adjustm e nt f o ur p r o g ra mmin g inst r u c t io n s p r o d uce lo ga r i t h mic t a p e r in cr e m e n t and de cr em e n t o f t h e w i p e r . th es e s e t t i n gs a r e ac t i va te d b y t h e 6 db i n cr e m en t a nd 6 db de cr e m e n t i n st r u c - tio n s (12, 13, 4, a nd 5). f o r exa m p l e , s t a r tin g a t zer o s c ale , exe c u t in g t h e i n cr em e n t i n s t r u c t io n 12 s e v e n t i m e s m o v e s t h e wi p e r in 6 db p e r s t ep f r o m 0% t o f u l l s c ale , r ab . t h e 6 d b in cr e m e n t i n s t r u c t io n do ub les t h e va l u e o f t h e rd a c r e g i st er co n t en t s ea ch tim e t h e co m m a n d i s e x ecu t ed . w h e n t h e wi pe r p o si t i o n is n e a r t h e maxi m u m s e t t i n g, t h e l a s t 6 db i n cr e m en t in s t r u c t io n c a us es t h e w i p e r t o g o t o t h e f u l l -s c a le 63 10 co de pos i ti o n . f u r t h e r 6 d b pe r in c r e m en t in s t r u cti o n s d o n o t c h a n g e th e wi pe r pos i tio n bey o n d i t s f u ll sc al e . the 6 db s t ep i n cr e m en ts and 6 db s t ep de cr e m e n ts a r e ac hieved b y s h if tin g t h e b i t in ter n al l y t o th e lef t o r r i g h t, r e sp e c t i vely . the fol l o w in g info r m a t io n ex plains t h e n o ni de a l 6 db step a d j u st men t u nder ce r t a i n con d i t io n s . t a b l e 8 i l l u s t ra t e s t h e op era t ion o f t h e s h if t i ng f u n c t i on o n t h e r d a c r e g i s t er da t a b i t s . e a ch t a b l e r o w r e p r es en ts a succes s i v e s h if t o p era t ion. n o te tha t t h e lef t -s hif t 12 a nd 13 ins t r u c t io n s w e r e m o d i f i ed s u c h t h a t , i f th e d a ta in th e r d a c r e g i s t e r i s eq ua l t o zer o an d t h e da t a is s h if t e d lef t , t h e r d a c r e g i st er is t h e n s e t t o c o de 1. s i mil a rly , if th e da t a in th e rd a c r e g i ster is g r ea t e r t h a n o r e q u a l to mids ca le a nd t h e d a t a is shif te d lef t , t h e n t h e da t a in t h e r d a c r e g i st er is a u to ma t i c a l l y s e t to f u l l s c a l e . this m a k e s th e l e ft- s h i ft fun c ti o n a s i d eal a l o g a ri th m i c a d j u s t m e n t as p o ssib le. the r i g h t - shif t 4 a nd 5 inst r u c t io n s a r e ide a l on ly if t h e ls b is 0 (ide al loga r i t h mic = n o er r o r). i f t h e lsb is a 1, t h e r i g h t-shif t f u nc t i o n ge ne r a te s a l i ne ar h a l f - l sb e r ror , w h i c h t r ans l a t e s to a n u m b er -o f- b i ts- d ep e n de n t loga r i t h mic er r o r , as s h o w n i n f i gur e 42. th e plo t s h o w s t h e er r o r o f t h e o dd n u m b ers o f b i ts f o r th e ad5233. tab l e 8. detail left-shift and right-shift fun c tion s for 6 db ste p i n cre m ent a n d decr ement l e f t - s h i f t r i g h t - s h i f t 00 0000 11 1111 00 0001 01 1111 00 0010 00 1111 00 0100 00 0111 00 1000 00 0011 01 0000 00 0001 10 0000 00 0000 11 1111 00 0000 left-shift (+ 6 db/ s tep) 11 1111 00 0000 right-shift (C6 db/ s tep) a c t u al co nfo r ma n c e t o a loga r i t h mic c u r v e b e t w e e n t h e da t a co n t e n ts i n t h e rd a c r e g i st er a nd t h e wi p e r p o si t i o n fo r e a ch r i g h t-sh if t 4 and 5 co mmand e x e c u t io n co n t a i n s a n er r o r o n ly fo r o dd n u m b ers o f b i ts. e v e n n u m b ers o f b i ts ar e ide a l . th e g r a p h i n f i g u re 4 2 show s pl ot s of l o g _ e r ror [ 2 0 l o g 10 (er r o r /co d e)] f o r th e ad5233. f o r exa m p l e , c o de 3 l o g_er r o r = 20 log 10 (0.5/3) = ?15.56 db , whic h is t h e w o rs t cas e . th e p l ot of l o g _ e r ror i s more s i g n i f i c an t a t t h e l o we r c o d e s . code 0 0 db ?1 0 ?5 0 ?4 0 ?3 0 ?2 0 ? 15.56db @ code 3 5 1 01 52 02 5 3 03 54 04 5 5 0 5 56 06 5 02794-a - 043 f i g u re 42. pl ot of l o g _ e r r o r conf o r m a nc e f o r o dd nu m b ers of bit s o n ly (even numbe r s of bits ar e id eal)
ad5233 rev. a | page 19 of 28 u s ing additio n al i n ter n al n o nvolatile eemem the ad5233 con t a i n s addi tio n al us er eemem r e g i s t ers f o r s t o r in g an y 8- b i t da t a . t a b l e 9 pr o v ides a n addres s ma p o f t h e in t e r n al st o r a g e r e g i s t ers sh o w n in t h e f u n c tio n a l b l o c k dia g ra m as eemem1, eemem2, a n d 1 1 b y t e s o f user eemem. table 9. ee me m ad dress ma p eemem umbe r addres s eemem co ntent fo r 1 0 0 0 0 rdac1 1, 2 2 0 0 0 1 rdac2 1, 2 3 0 0 1 0 rdac3 1, 2 4 0 0 1 1 rdac4 1, 2 5 0100 o1 and o2 3 6 0 1 0 1 user1 4 7 0 1 1 0 u s e r 2 1 5 1 1 1 0 u s e r 1 0 1 6 1 1 1 1 u s e r 1 1 __ __ __ __ __ __ __ __ __ __ __ __ __ _ _ _ _ _ _ _ _ 1 r d a c da t a st or e d i n t h e ee me m loca t i on i s t r a n sf e r r e d t o t h e r d a c r e g i st er a t po w e r - on , or wh en in st ruc t i on 1, in s t ruc t i on 8, a n d pr ar e ex ecut ed . 2 ex ecut i o n o f in st r u c t i o n 1 l e a v es t h e devi c e i n t h e r e a d m o de po w e r c o n s um pt i o n st a t e . a f t e r t h e la st in st ru c t i o n 1 i s ex ecut e d , t h e user sh ou ld per f o r m a n o p , in st ruc t i on 0, t o r e t u rn t h e devi c e t o t h e lo w po w e r i d li n g st a t e . 3 o1 a n d o2 da t a st or e d i n ee me m loca t i on s i s t r a n sf e r r e d t o t h e c o rr esp o n d - in g dig i t a l r e g i st er a t po w e r - on , or wh en i n st ruc t i on s 1 an d 8 a r e ex ecut e d . 4 user x a r e i n t e rn a l n o n v ola t i l e e e m e m r e g i st ers a v a i l a b le t o st or e a n d re tr ie v e co ns tan t s and o the r 8-bit inf o rma t io n us ing i n s t ruc tio n 3 and in st ruc t i on 9, r e spe c t i v e ly . rd a c str u c t ure t h e p a t e n t - p e n d i ng r d a c c o n t ai ns m u lt i p l e st r i ng s of e q u a l r e sis t o r s e g m en ts, wi t h an a r ra y o f a n alog swi t ch es tha t ac t as th e wi pe r co nn e c ti o n . th e n u m b e r o f posi ti o n s i s th e r e so l u ti o n o f th e device . th e ad5233 has 64 co nnec t io n p o in ts, al lo win g i t t o p r o v ide bet t e r tha n 1.5% s e t a b ili t y r e s o l u tion. f i gur e 43 s h o w s a n eq ui val e n t s t r u ct ur e o f th e co nn ectio n s bet w e e n t h e th r e e t e rm i n als o f th e r d a c . th e sw a a nd s w b are a l w a y s on , while t h e swi t ches sw(0) t o sw(2 n ? 1 ) are on , one a t a t i me, dep e n d in g on t h e r e sist an c e p o si t i o n d e co de d f r o m t h e d a t a b i ts. b e c a us e t h e sw i t ch is n o t i d e a l , t h er e is a 1 5 ? wi p e r re s i st anc e , r w . w i p e r re s i st anc e is a f u nc t i on of su p p ly vol t age a nd t e m p er a t ure . the lo w e r t h e s u p p l y v o l t a g e o r t h e hig h er t h e t e m p era t ur e , t h e hig h er t h e r e su l t in g wi p e r r e sis t an ce . u s ers shou l d b e a w are of t h e w i p e r re s i st a n c e dy n a m i c s , i f a c c u r a te pre d i c t i on of t h e output re s i st a n c e i s n e e d e d . sw (1) sw (0) sw b b r s r s sw a sw(2 n ? 1) a w sw(2 n ? 2) r dac wiper register and decoder r s = r ab /2 n r s digit al c ircuit r y o mitted fo r c larit y 02794-a - 044 f i gure 43. equiv a le nt r d a c struc t ure progr a mm ing the v a riable resi st or r h eos t at ope r ation the n o minal r e sis t a n ce o f t h e rd a c b e tw e e n t e r m inals a and b, r ab , is a v a i la ble wi t h 10 k?, 5 0 k?, a nd 100 k? wi t h 6 4 p o s i t i ons ( 6 - b it re s o lut i on ) . t h e f i n a l d i g i t ( s ) of t h e p a r t n u m b er det e r m ine t h e n o minal r e sis t a n ce val u e, fo r exa m ple , 10 k? = 10; 50 k? = 50; 100 k? = 100. the 6- b i t d a t a - w o r d in t h e rd a c la tch is d e c o de d to s e le c t on e of t h e 6 4 p o ss i b l e s e tt i n g s . t h e f o l l ow i n g d i s c u s s i on d e s c r i b e s th e calcula t i o n o f r e si s t a n ce r wb a t dif f er en t co des o f a 10 k? pa r t . f o r v dd = 5 v , th e w i pe r s f i r s t co nn ecti o n s t a r t s a t t e r m inal b f o r da ta 0x00. r wb ( 0 ) is 15 ? b e c a us e o f t h e w i p e r r e sist a n c e an d b e ca us e i t is i nde p e nden t o f t h e n o m i na l r e sis t a n c e . th e s e con d co nne c t i o n is t h e f i rs t t a p p o in t, w h er e r wb (1) becom e s 156 ? + 15 ? = 171 ? f o r da ta 0x01. th e third co nne c t io n is t h e n e xt t a p p o in t r e p r es en t i n g r wb (2) = 321 ? + 15 ? = 327 ? f o r da t a 0x02 an d s o o n . e a c h ls b da ta va l u e i n c r e a s e m o v e s t h e w i pe r u p th e r e s i s t o r l a d d e r u n t i l th e la s t ta p p o in t is r e ache d a t r wb (63) = 9858 ?. s e e f i gur e 43 f o r a s i m p l i f i ed di a g ra m o f th e eq ui val e n t rd a c ci r c ui t . w h e n r wb is us ed , t e r m inal a can b e lef t f l o a tin g o r tie d t o t h e wi p e r . code (decimal) 100 75 0 06 16 r wa (d), r wb (d) (% of full-s cale r ab ) 33 48 4 50 25 r wb r wa 02794- a- 045 f i g u re 44. r wa (d) and r wb (d) vs . d e cim a l code
ad5233 rev. a | page 20 of 28 t h e g e n e ral eq ua ti o n tha t d e t e r m in e s th e p r ogra mm ed o u t p u t r e sist a n c e b e twe e n w an d b is w ab wb r r d d r + = 64 ) ( ( 1 ) wher e: d i s th e deci m a l eq u i v a le n t o f th e da ta co n t a i n e d in th e r d a c re g i ste r . r ab is th e n o m i nal r e sis t a n ce b e tw een t e r m ina l s a a n d b . r w is t h e wi p e r r e sist a n c e . f o r exa m ple , t h e o u t p u t r e sist an ce v a l u es in t a b l e 10 a r e s e t for th e g i v e n rd a c la t c h co des wi th v dd = 5 v (a p p lies t o r ab = 1 0 k? di g i t a l p o te n t i o me te rs ) . table 10. r wb ( d ) at selected cod e s for r ab = 10 k? d (de c ) r wb (d) (?) output state 6 3 9 8 5 8 f u l l s c a l e 3 2 5 0 1 5 m i d s c a l e 1 1 7 1 1 l s b 0 15 zero scale (wipe r contact resistor) n o t e tha t in t h e zer o -s cale co n d i t io n a f i ni t e wi p e r r e sis t a n c e o f 15 ? is p r es en t. c a r e sh o u ld b e t a k e n t o li mi t t h e c u r r en t f l o w betw een w an d b in this sta t e t o n o m o r e tha n 2 0 m a t o a v o i d deg r ada t ion o r p o ssi b le de st r u c t io n o f t h e in t e r n a l swi t ch es. l i k e t h e me chanical p o t e n t iomet e r t h a t t h e rd a c r e places, t h e ad5233 p a r t is t o tal l y symm etr i cal . th e r e sis t an ce betw een w i per w a n d t e rm i n al a also p r od u c e s a d i gi tall y c o n t r o ll ed co m p lem e n t a r y r e sis t a n c e , r wa . f i gur e 44 sh o w s t h e sy mm et r i - cal p r og ra m m a b i li ty o f th e va r i o u s t e r m inal co nn ec t i o n s. w h en r wa is used , t e r m in al b c a n be l e f t f l o a tin g o r tied t o t h e wi p e r . s e t t in g t h e r e sist a n ce val u e fo r r wa st ar ts a t a max i m u m va l u e o f r e sist a n ce and de cr e a s e s as t h e da ta loa d e d in th e la t c h i s in cr e a s e d in va lue . t h e g e n e ral tra n s f e r eq u a ti o n f o r th i s o p e r a t i o n i s w ab wa r r d d r + ? = 64 64 ) ( (2) f o r exa m ple , t h e o u t p u t r e sist an ce v a l u es in t a b l e 11 a r e s e t for th e rd a c la t c h cod e s wi th v dd = 5 v (a p p lies to r ab = 10 k? di g i t a l p o te n t i o me te rs ) . table 11. r wa (d) at selected cod e s for r ab = 10 k? d (de c ) r wa (d) (?) output state 6 3 1 7 1 f u l l s c a l e 3 2 5 0 1 5 m i d s c a l e 1 9 8 5 8 1 l s b 0 10015 zero scale c h a n n e l - to -channel r ab m a t c hin g is bet t er tha n 1% . the c h a n g e in r ab wi t h t e m p era t ur e has a 6 00 p p m / c t e m p era t ur e co ef f i cien t. progr a mm ing the po tent iome t e r divi der voltage o u tp ut ope r ation the di g i t a l p o te n t i o me te r c a n b e c o nf i g u r e d to ge ne r a te an output vo lt ag e at t h e w i p e r te r m i n a l t h a t i s prop or t i on a l to t h e in p u t v o l t a g es a p plie d t o t e r m i n a l s a an d b . f o r exa m ple , co nne c t in g t e r m ina l a t o 5 v a n d t e r m ina l b t o g r o u n d p r o d uces a n ou t p u t v o l t a g e a t t h e wi p e r t h a t can b e an y val u e f r o m 0 v t o 5 v . e a c h ls b o f v o l t a g e is e q ual t o t h e v o l t a g e a p plie d acr o ss t e r m ina l ab divi de d b y t h e 2 n po s i t i o n r e s o l u - t i on of t h e p o te n t i o me te r d i v i d e r . b e ca us e ad523 3 ca n als o be s u p p lied b y d u al su p p lies, th e ge ne r a l e q u a t i o n d e f i n i ng t h e o u tput vo lt ag e a t v w wi th r e s p ect t o g r o u n d fo r an y g i v e n in p u t vol t a g es a p plie d to t e r m ina l s a an d b i s b ab w v v d d v + = 64 ) ( ( 3 ) eq u a ti o n 3 as s u m e s tha t v w is b u f f er e d s o t h a t t h e ef fe c t o f wi p e r r e sist an ce is minimi ze d . o p era t ion o f t h e dig i t a l p o ten t i - o m e t er in divider m o de r e su l t s in m o r e acc u ra te o p era t ion o v er t e m p era t ur e . h e r e , t h e o u t p u t vol t a g e is de p e n d en t on t h e ra t i o o f t h e in t e r n al r e sist o r s a n d n o t t h e a b s o l u t e v a lue; t h er efo r e , t h e dr if t im p r o v es t o 15 p p m/ c . th er e is n o v o lt a g e p o la r i ty r e s t r i ctio n between t e r m in als a, b , a n d w as lo n g as t h e te r m i n a l volt age ( v te rm ) s t a y s w i t h in v ss < v te rm < v dd . progr a mming e amples the fol l o w in g pr og ra mmin g exa m ples i l l u st ra te a typ i cal s e q u en ce o f ev en ts fo r va r i o u s f e a t ur es o f the ad5233. s e e t a b l e 7 fo r t h e i n st r u c t io n s an d da t a -w o r d fo r m a t . the in st r u c t io n n u m b ers, addr ess e s, a n d d a t a a p p e a r in g a t s d i and s d o p i n s a r e in h e xadecim a l f o r m a t . table 12. scratchpad progra mming s d i s d o a c t i o n 0 x b 0 1 0 0 x x x x x writes data 0x10 into rdac1 re gister, wiper w1 move s to 1/4 full-sca l e position. table 13. i n cre m enting rda c 1 followed by storing the wiper setting t o eeme m 1 s d i s d o a c t i o n 0 x b 0 1 0 0 x x x x x writes data 0x10 into rdac1 re gister, wiper w1 move s to 1/4 full-sca l e position. 0 x e 0 x x 0 x b 0 1 0 increments rdac1 register by one to 0x11. 0x e 0 x x 0 x e 0 x x increments rdac1 register by one to 0x 12. continue until desired wiper position is reac h e d. 0x 2 0 x x 0 x x x x x stores rdac1 register data into eemem1. optionally tie wp to gnd to protect eemem values.
ad5233 rev. a | page 21 of 28 end u ran c e quan t i f i es t h e ab i l i t y o f t h e flash/e e m e m o r y t o b e c y cle d t h r o ug h ma n y p r og ra m, r e ad , a n d eras e c y cles. i n r e al t e r m s, a sin g le en d u ran c e c y c l e is co m p ose d o f f o ur in d e p e n d - en t, s e q u en t i al e v en ts: the eemem va l u e fo r rd a c c a n be r e s t o r e d b y p o w e r - o n , b y st rob i ng t h e pr p i n, o r b y p r o g r a mming, as sh o w n in t a ble 14. table 14. restoring the eeme m 1 value to th e rdac1 r e gister s d i s d o a c t i o n 0x 1 0 x x 0 x x x x x restores the eemem1 value to the rdac1 register. 0 x 0 0 x x 0 x 1 0 x x nop. recommended step to minimize power c o nsump t ion. ? i n i t ial p a ge eras e s e q u e n ce ? re a d /v er if y s e quen ce ? b y t e p r ogra m s e q u en ce ? s e con d r e a d /v e r if y s e q u en ce table 15. usin g left-shift by one to increm ent 6 db ste p d u r i n g r e liab i l i t y q u a l if ica t io n, flash/ee m e m o r y is c y cle d f r o m 0x00 t o 0x3f un til a f i rs t f a il is r e co r d ed , s i g n if yin g t h e end u ran c e li mi t o f t h e o n -chi p flash/ee m e m o r y . s d i s d o a c t i o n 0x c 0 x x 0 x x x x x moves the wipe r to double the present data contained in the rdac1 re gister. a s indic a t e d in th e s p ecif ic a t ion s s e c t ion, th e ad5233 flash/ee m e m o r y end u ran c e q u a l if ic a t ion has b e e n ca r r i e d o u t i n acco r d an c e wi t h jed e c s p ecif ica t ion a117 o v er th e ind u s t r i al t e m p era t ur e ra ng e o f ?40c t o +85c. the r e su l t s al lo w t h e sp e c if ic a t ion o f a minim u m e n d u ra n c e f i gur e o v er su p p ly a n d t e m p era t ur e o f 100,000 c y c l es, wi t h an en d u ran c e f i gur e o f 700,000 c y c l es bein g typ i cal o f op era t ion a t 25c. table 16. stori n g ad ditional user data in e e mem s d i s d o a c t i o n 0x 3 5 a a 0 x x x x x stores data 0xaa in the extra eemem6 locatio n user1. ( a llowa ble to ad d r ess in 11 location s with a maximu m of 8 bits of data.) 0 x 3 6 5 5 0 x 3 5 a a stores data 0x55 in the extra eemem7 locatio n user2. ( a llowa ble to ad d r ess in 11 location s with a maximu m of 8 bits of data.) ret e n t ion q u a n t i f i es t h e ab i l i t y o f t h e flash/ee m e m o r y t o r e ta in i t s p r og ra m m e d da ta o v er tim e . a g a i n, the ad5233 has b e e n q u a l if ie d i n acco rdan ce wi t h t h e fo r m a l jed e c ret e n t ion lifetim e s p ecif ica t ion (a117) a t a s p ecif ic j u n c tio n t e m p er a t ure (t j = 55c). a s p a r t o f t h is q u a l if ica t ion p r o c e d ur e , t h e flash/e e m e m o r y is c y cle d to its sp e c if ie d e n d u r a n c e li mi t, des c r i b e d a b o v e , b e fo r e da t a r e t e n t io n is cha r ac t e r i ze d . this m e a n s t h a t th e fla s h/ ee m e m o r y i s g u a r a n t eed t o r e ta in i t s da ta f o r i t s full s p e c i f i e d re te n t i o n l i f e t i me e v e r y t i me t h e f l a s h / e e me mor y i s r e p r ogra m m ed . i t s h o u ld also b e n o t e d tha t r e ten t io n lif e tim e , base d o n an ac tiva tio n en er g y o f 0.6 ev , d e ra t e s wi t h t j as s h o w n in f i gur e 45. f o r exa m p l e , th e da ta is r e t a in ed f o r 100 yea r s a t 55c o p era t ion, b u t r e d u ces t o 15 yea r s a t 85c o p era t ion. b e yond t h e s e limi ts, t h e p a r t m u st b e r e p r og ra mm e d so th a t t h e d a ta ca n be r e s t o r ed . table 17. readi n g back data f r om m e mor y l o cations s d i s d o a c t i o n 0x 9 5 x x 0 x x x x x prepares data read from user1 eemem locatio n . 0 x 0 0 x x 0 x 9 5 a a nop instruction 0 send s a 16-bit word out of sdo, where the last 8 bits contain the contents of the use r 1 locatio n . t h e nop command e n sures that the device returns to the idle power dis s ipati o n state. ta ble 18. rea d i n g ba ck wi per set t i ngs t j junct i o n t emper a t u r e ( c) 300 250 0 40 ret e nt i o n (years) 200 150 100 50 50 60 70 80 90 100 110 adi typical performance at t j = 55 c 02794- a- 046 s d i s d o a c t i o n 0xb020 0xxxxx writes rdac1 t o midscale. 0 x c 0 x x 0 x b 0 2 0 doubles rdac1 from mid scale t o full scal e (left-shift instruction). 0x a 0 x x 0 x c 0 x x prepares readin g the wiper setting from the rdac1 regis t er. 0x xxxx 0x a03f reads back fu ll-scale value from sdo. fl ash/eemem reliabilit y the flash/ee m e m o r y a r ra y o n th e ad5233 is f u l l y q u alif ied f o r t w o ke y f l a s h / e e me mor y c h ar a c te r i s t i c s , f l a s h / e e me mor y c y clin g end u ra nce an d fl ash/ee m e m o r y da t a ret e n t ion. f i gure 45. f l ash/ee memor y d a ta rete ntion
ad5233 rev. a | page 22 of 28 appli c a t ions bipol a r o p er a t ion from du al s u pplies the ad5233 can b e o p er a t e d f r o m d u al s u p p lies 2.5 v , whic h ena b les co n t r o l o f g r o u n d -r efer en ce d ac sig n als o r b i p o l a r o p era t ion. a c sig n als as hig h as v dd /v ss ca n b e a p plie d dir e c t ly a c r o s s t e rm i n als a C b wi th o u t p u t tak e n f r o m t e rm i n al w . s e e f i gur e 46 f o r a typ i cal cir c ui t co nn ec t i o n . 2.5v p-p ad523 3 v ss gnd sdi clk ss sclk mosi gnd v dd c 1.25v p-p v dd +2.5v ?2.5v cs d = midscale a w b 02794-a - 047 f i g u re 46. bipol a r o p er at ion f r om d u al sup p l i es g a i n co n t r o l co m p e n s a t i o n a dig i t a l p o t e n t io m e t e r is co mm o n ly us e d in g a in con t r o l such as the n o n i n v er tin g ga in a m p l if ier s h o w n in f i gur e 47. u1 v o r2 02794-a - 048 100k ? v i r1 33.2k ? c1 35pf w ba c2 10pf f i g u re 47. t y pic a l n o ni nve r t i ng g a in a m pl if ie r w h en rd a c b t e r m inal p a rasi t i c ca p a c i tan c e is co nnec t e d t o th e o p a m p n o ni n v e r ti n g n o d e , i t in tr od u c e s a 0 f o r th e 1/ b o t e r m wi th 20 db /dec, while a typ i cal o p a m p gbp has ?20 db/de c ch arac ter i st ics. a large r2 a n d f i ni te c1 can c a us e this zer o s f r eq uen c y t o fal l w e l l be lo w t h e cr os s o v e r f r eq uen c y . ther efo r e , t h e ra t e o f closur e b e co m e s 40 db/de c , a n d t h e syst em as a 0 phas e ma rg i n a t t h e cr oss o v e r f r e q uen c y . th e o u t p u t can r i n g o r os cil l a t e , if an in p u t is a r e c t a n gu la r p u ls e o r s t ep f u n c tio n . s i m i la r l y , i t is also lik e l y t o r i n g w h en swi t c h in g betw een tw o ga in val u es; this is eq ui valen t t o a st o p c h a n g e a t th e in p u t . dep e n d in g o n th e o p am p gb p , r e d u cin g t h e f e ed back r e sis t o r mig h t exte n d t h e zer o s f r e q uenc y fa r en o u g h to o v er co m e t h e p r ob lem. a b e t t er a p p r o a ch is to in cl ude a com p en s a t i o n ca p a c i t o r , c2, t o can c e l t h e ef f e c t ca us e d b y c1. op tim u m co m p e n s a t i o n o c c u rs w h e n r1 c1 = r2 c2. this is n o t an opt i on b e c a u s e of t h e v a r i a t i o n of r 2 . a s a r e su lt, o n e ca n us e t h e r e l a t i o n shi p a b o v e and s c ale c2 as if r2 w e r e a t i t s maxim u m va l u e . d o in g t h is mig h t o v er co m p e n - s a t e a n d com p ro mis e t h e p e r f o r ma n c e w h en r 2 is s e t a t lo w val u es. on t h e ot h e r hand , i t a v oids t h e r i n g i n g o r os ci l l a t io n a t t h e w o rst cas e . f o r cr i t ica l a p pl ica t ion s , c2 sh ou ld b e fo u n d em p i r i cal l y t o sui t t h e n e e d . i n g e n e ral, c2 i n t h e ra n g e o f pf is us ual l y ade q u a te fo r t h e co m p e n s a t i on. s i m i la r l y , w a n d a t e rm i n al ca pa c i ta n c e s a r e co n n ec t e d t o th e o u t p ut (n ot sh o w n); t h eir ef fe c t a t t h is n o de is less sig n if ican t a n d t h e com p ens a t i on can b e a v o i de d i n m o st c a s e s. high vol t a g e oper a t ion t h e dig i tal p o t e n t io m e t e r ca n b e p l ace d dir e c t ly in the f eedback o r in p u t p a th o f a n o p am p f o r ga in co n t r o l , p r o v id ed tha t t h e v o l t a g e acr o ss t e r m inals a C b , w C a, o r w C b do es n o t exce e d |5 v|. w h en hig h v o l t a g e ga in is n e e d e d , us ers sh o u ld s e t a f i xe d ga in in a n o p am p o p era t e d a t high v o l t a g e an d let the d i g i tal p o te n t i o me te r c o n t rol t h e a d j u s t abl e i n pu t . f i g u re 4 8 shows a si m p le im p l em en ta ti o n . r2 r 5v ad5233 a w b 15v v+ v? v o 0 to 15v 02794-a - 049 a2 ? + c f i g u re 48. 1 5 v v o lt ag e sp an cont ro l s i m i l a rl y , a co m p en s a tio n ca p a c i t o r c m i g h t be n e e d e d t o dam p e n t h e p o ten t ia l r i n g in g w h e n t h e dig i t a l p o t e n t iom e t e r cha n g e s st eps. this ef fe c t is p r o m i n en t w h e n st ra y ca p a c i t a n c e a t t h e in v e r t e d n o de i s a u g m en t e d b y a la r g e f eed ba ck r e si s t o r . u s ual l y , a f e w p f ca p a ci t o r c is adeq u a te t o co m b a t t h e pro b l e m . da c f i gur e 49 s h o w s a uni p ola r 8-b i t d a c usin g t h e ad5233. th e b u f f e r i s n eeded t o d r i v e v a ri o u s loa d s. ad5233 v+ v? ad8601 w a1 v in v out gnd ad1582 02794-a - 050 5v 5v u1 3 a b v o 1 2 f i g u re 49. u n ipol ar 8-b i t da c
ad5233 rev. a | page 23 of 28 bipol a r progr a mmable gain amplifier ther e a r e s e v e ral wa ys t o achi e v e b i p o la r ga i n . f i gur e 50 sh o w s o n e v e rs a t i l e i m plem e n t a t i o n . dig i t a l p o t e n t iomet e r u1 s e ts t h e ad j u st m e n t ra ng e; t h e wi p e r v o l t a g e v w2 can, t h er efo r e , b e p r ogra m m e d bet w een v i an d ? kv i a t a gi v e n u2 set t in g. v+ v? op2177 v o v+ v? op2177 ad5233 ad5233 v i a1 w1 b1 ?kv i a2 b2 w2 v dd v ss r1 02794-a - 051 r2 v dd v ss a1 u2 a2 u1 c f i g u re 50. bipol a r pr og r a mm ab le g a i n a m pl if ie r c o nf igur in g a2 as a n o ni n v er t i n g a m plif ier yi elds a line a r tra n s f e r fu n c ti o n : ? ? ? ? ? ? ? + ? ? ? ? ? ? + = k k d2 r1 r2 v v i o ) 1 ( 64 1 ( 4 ) wher e: k i s th e ra ti o o f r wb /r wa tha t is set b y u1. d is th e decim a l eq ui valen t o f th e in p u t co de . i n t h e sim p ler (a nd m u ch m o r e us ual) cas e w h e r e k = 1, a p a ir of m a tc he d re s i stor s c a n re pl a c e u 1 . e q u a t i on 4 c a n b e sim p lif i e d t o ? ? ? ? ? ? ? ? ? ? ? ? ? + = 1 64 2 1 2 d r1 r2 v v i o ( 5 ) t a b l e 19 sh o w s t h e r e s u l t o f ad j u s t in g d wi t h a 2 co nf igur e d as a uni t y ga in, a ga in o f 2, a n d a ga in o f 10. t h e r e sul t is a b i p o l a r a m p l if ier wi t h lin e a r l y p r og ra mma b l e ga in an d 64-s t ep re s o lut i on . table 19. result of bip o lar ga in amp l ifier d r1 = , r2 = 0 r1 = r2 r2 = 9 r1 0 ? 1 ? 2 ? 1 0 1 6 ? 0 . 5 ? 1 ? 5 3 2 0 0 0 4 8 0 . 5 1 5 6 3 0 . 9 6 8 1 . 9 3 7 9 . 6 8 0 progr a mm able l o w - p a ss fil t er the ad5233 dig i tal p o t e n t iomet e r can b e us ed t o co n s tr uc t a s e con d -o r d er s a l l en-k e y lo w-p a s s f i l t er , as sh o w n in f i gur e 51. a b v i ad 8601 +2.5v v o ganged together ?2 .5 v v+ v? w r r2 02794-a - 052 r1 a b w r c1 c2 u1 f i gure 51. s a l l en- k ey l o w - p a ss f ilter the desig n e q u a t i o n s a r e 2 2 2 o o o i o s q s v v + + = (6) r1r2c1c2 o 1 = (7) q = r2c2 1 r1c1 + 1 (8) wher e: q is t h e q fac t or . v o is th e r e so nan t f r eq uen c y . r1 an d r2 are r wb1 an d r wb2 , r e s p e c t i v e l y . t o achi e v e maxi mal l y f l a t b a n d wi d t h w h er e q = 0.707, let c1 be t w ice t h e si ze o f c2 and let r1 eq u a l r2 . u s e r s ca n f i r s t s e l e ct co n v e n ien t val u es fo r t h e ca p a c i t o rs a n d t h en gan g an d m o v e r1 an d r2 t o g e t h er t o ad j u s t t h e ?3 db co r n er f r eq uen c y . i n s t r u c t io n s 5, 7, 13, a n d 15 o f th e ad5233 ma k e th es e c h a n g e s s i m p le t o im p l em en t . progr a mm able st a t e- v a riable fil t er on e o f t h e s t anda r d c i r c ui ts us ed t o g e n e ra t e a lo w-p a s s , high- p a s s , o r b a nd-p as s f i l t er is t h e st a t e-va r i ab le ac t i v e f i l t er . th e ad5233 dig i tal p o t e n t iom e t e r a l lo ws f u l l p r og ra mmab i li ty o f t h e f r e q ue n c y , t h e ga i n , an d t h e q o f t h e f i l t er ou t p u t s. f i gur e 52 s h o w s a f i l t er cir c ui t usin g a 2.5 v vir t ual g r o u nd , which al lo ws a 2.5 v p e a k i n p u t and o u t p ut sw ing. rd a c 2 a n d r d a c 3 s e t t h e l p , h p , a n d b p c u t o f f a n d c e n t e r f r e q u e n c i e s , r e s p e c t i v e l y . r d ac 2 a n d r d ac 3 s h o u l d b e p r o g r a m m e d w i t h t h e s a m e d a t a ( a s w i t h g a ng e d p o te n t i o me te rs ) to mai n t a i n t h e b e s t c i rc u i t q .
ad5233 rev. a | page 24 of 28 a3 a2 a1 0.01 f 0.01 f rdac3 low-pass band-pass high-pass 02794- a - 053 rdac2 b rdac4 b v in b rdac1 2. 5v op279 2 r2 10k ? r1 10k ? a3 b f i g u re 52. p r og r a m m ab le st abl e - v ar ia ble f i l t er the t r a n sfer f u n c t i on o f t h e b a nd-p as s f i lt er is 2 2 o o o o i bp s q s s q a v v + + = (9) wher e a o is t h e ga in. fo r r wb2(d2) = r wb3(d3) , r1 = r2 , a n d c1 = c2 : c1 r wb2 o 1 = ( 1 0 ) wa1 wb1 o r r a = ( 1 1 ) r1 r r r q wb1 wb4 wa4 = ( 1 2 ) f i g u re 5 3 show s t h e me a s u r e d f i lte r re sp ons e a t t h e b a n d - p a s s output a s a f u nc t i on of t h e r d a c 2 an d r d a c 3 s e tt i n g s , w h i c h p r o d uce a ran g e o f cen t er f r e q uen c ies f r o m 2 kh z t o 20 kh z. the f i l t er ga i n r e s p o n s e a t t h e b a nd-p as s o u t p u t is s h o w n i n f i gur e 54. a t a c e n t er f r eq uen c y o f 2 kh z, t h e gain is ad j u s t e d o v er th e ?20 db t o +20 db ra n g e , det e r m in e d b y rd a c 1. cir c ui t q is ad j u s t ed b y rd a c 4 a n d rd a c 1. the s u i t a b le o p a m ps f o r this a p p l ica t ion a r e op4177, ad8604, o p 279, a n d ad824. 02794-a - 054 40 20 100 1k 10k 100k 200k frequency (hz) amp l itude (db) 0 ?20 ?40 ?60 ?80 20 20k ?1 6 * f i gure 53. p r ogr a mmed center f r eq ue nc y band- p ass resp onse 02794-a - 055 40 20 100 1k 10k 100k 200k frequency (hz) amp l i t ude (db) 0 ?20 ?40 ?60 ?80 20 * 2.0k ? 19.01 f i gur e 5 4 . p r o g r a mm ed a m pli t ude band-p a ss resp o n se progr a mm able oscill a t or i n a clas sic w i en-b r i dg e os cil l a t o r , s h o w n in f i gur e 55, th e w i en n e t w o r k ( r , r , c , c ) p r o v i d e s p o s i t i v e f e e d b a c k , w h i l e r 1 a n d r 2 p r o v i d e n e ga ti v e f e e d ba c k . a t th e r e so na n t f r eq u e n c y , f o , t h e o v eral l phas e s h if t is zer o , and t h e p o si t i v e fe e d b a ck c a us es t h e cir c ui t t o oscil l a t e . i f th e o p am p is c h osen wi th a r e l a ti ve l y hig h g a i n b a n d w i d t h pro d u c t , t h e f r e q u e nc y re sp ons e of t h e op a m p ca n b e neg l e c te d . +2.5v op1177 v+ v? v o ? 2.5v r2a 2.1k ? d1 d2 02794-a - 056 r2b 10k ? vn r1 1k ? a b w r = r' = r2b = 1/4 ad5233 d1 = d2 = 1n4148 c' 2.2nf r' 10k ? ab w vp c 2. 2n f r 10k ? a b w u1 amplitude adjustment frequency adjustment f i g u re 55. p r og r a m m ab le o s ci ll at or wi t h a m pl it ude cont rol wi t h r = r , c = c , and r2 = r2a // ( r2b + r diode ), th e os ci l l a t ion f r e q uen c y is rc o 1 = or rc f o = 2 1 (13) wher e r is e q ua l t o r wa su ch t h a t ab r d r 64 64 ? = ( 1 4 )
ad5233 rev. a | page 25 of 28 a t r e so n a n c e , set t i n g 2 = r1 r2 ( 1 5 ) b a lan c es t h e b r idg e . i n p r ac t i ce , r2 / r1 sh o u ld b e s e t s l ig h t l y la r g e r th a n 2 t o e n s u r e th a t th e oscilla t i o n ca n s t a r t . o n th e o t h e r hand , t h e al t e r n a t e t u r n -on o f t h e dio d es d1 an d d2 en s u r e s t h a t r1 / r2 i s s m a l l e r t h an 2 mome n t ar i l y and, t h er efo r e , s t a b i l i z es t h e os ci l l a t i o n . on ce t h e f r e q uen c y is s e t, t h e os ci l l a t ion am pli t ude can b e tu r n e d by r2b , b e c a u s e d d o v r2b i v + = 3 2 ( 1 6 ) v o , i d , a n d v d a r e in ter d ep e n den t va r i a b les. w i t h p r o p er se l e cti o n o f r2b , a n eq uil i b r i u m is r e ac h e d s u c h tha t v o co n v erg e s. r2b ca n b e in s e r i es wi t h a dis c r e te resisto r to in cr eas e t h e am p l i t ude , b u t t h e t o tal r e sis t an ce ca nn o t be t o o la rge t o s a t u ra te t h e o u t p ut. i n t h is co nf igura t ion, r2b can b e ad j u ste d f r o m mini m u m to f u l l s c a l e wi t h am pli t ude va r i e d f r o m 0.6 v t o 0.9 v . u s in g 2. 2 nf f o r c a n d c, 10 k? d u al dig i t a l p o t e n t iom e t e r , wi t h r and r set to 8 k?, 4 k?, a n d 700 ?, os cil l a t io n o c c u rs a t 8.8 kh z, 17.6 kh z, a n d 100 kh z, re sp e c t i vely ( s e e f i g u re 5 6 ) . 1v / d i v r = 8. 06k ? f= 8 . 8 k h z r = 4. 05k ? f= 1 7 . 6 k h z r= 6 7 0 ? f = 1 02k hz 1v / d i v 1v / d i v 02794-a - 057 f i g u re 56. p r og r a m m ab le o s ci ll at i o n i n bo th cir c ui ts (s h o wn in f i gure 51 a n d f i gur e 55), th e f r eq uen c y t u ning r e q u ir es tha t bo th rd a c s b e ad j u s t e d t o t h e s a me s e t t in gs. b e ca us e t h e two chan n e ls mig h t b e ad j u ste d on e a t a t i m e , an in ter m e d i a t e st a t e o c c u rs t h a t mig h t n o t b e accep t ab le f o r s o m e a p p l ica t ions. of co urs e , th e in cr em en t/ decr em en t al l ins t r u c t io n s (5, 7, 13, a n d 15) ca n be us e d . dif f er en t de vices ca n also be us ed in da isy-c h ain m o de so tha t p a r t s ca n be p r og ra mm e d t o t h e s a me s e t t in g sim u l t an e o us l y . progr a mm able v o l t a g e source with bo osted o u tput fo r ap p l i c at i o n s t h at r e q u i r e h i g h c u r r e n t a d j u s t m e nt , s u c h a s a las e r dio d e dr i v er o r t u na b l e las e r , a b o os t e d v o lt a g e s o ur ce ca n be co n s i d e r ed (see f i g u r e 57). ad5233 v+ v? w u2 ad8601 a b v in v out r bias i l signal c c ld 2n7002 02794-a - 058 f i g u re 57. p r og r a m m ab le bo os te r v o lt ag e s o u r c e i n t h is cir c ui t, t h e i n ver t in g in pu t o f t h e o p am p fo r c es t h e v ou t t o b e e q ual t o t h e wi p e r v o l t a g e s e t b y t h e dig i t a l p o t e n t iom e ter . the lo ad c u r r en t is t h e n de li v e re d b y t h e s u p p ly vi a t h e n-c h fet n 1 . n 1 p o w e r h a nd l i ng m u st b e a d e q u a te t o d i ss ip a t e (v i ? v o ) i l p o w e r . this cir c u i t can s o ur ce a maxim u m o f 100 ma wi t h a 5 v s u p p l y . f o r p r ecisio n a p p l ica t ion s , a v o l t a g e r e f e r e n c e s u c h as ad r421, ad r03, o r adr370 can b e a p p l ied a t t e r m inal a o f th e dig i t a l p o te n t i o me te r . progr a mm able current source a p r og ra mma b l e c u r r en t s o ur ce ca n b e im ple m en t e d wi t h t h e cir c ui t sh o w n in f i gur e 58. v+ v? op1177 u2 vin sl eep ref191 gnd v out 3 2 4 6 u1 c1 1 f ad5233 w a b r s 102 ? r l 100 ? v l i l +5v ? 2 . 048v t o v l ?5v 0 t o (2.048 + v l ) +5v + ? 02794-a - 059 f i g u re 58. p r og r a m m ab le cur r ent s o u r c e ref191 is a uniq ue lo w s u p p l y h e adr o o m p r ecisio n r e f e r e n c e tha t c a n de li v e r th e 20 ma n e e d ed a t 2.048 v . th e lo ad c u r r en t is sim p ly t h e v o lt a g e acr o s s t e r m inals b t o w of t h e dig i t a l p o te n t i o me te r d i v i d e d b y r s . the cir c ui t is si m p le , b u t b e a w a r e t h a t t h er e a r e tw o is s u es. f i rs t, d u al-s u p ply o p a m ps a r e ide a l, b e ca us e t h e g r o u n d p o t e n t ial o f re f191 ca n s w in g f r o m ?2.048 v a t zer o s c ale t o v l a t f u l l s c ale o f t h e p o t e n t iom e ter s e t t i n g. a l t h oug h t h e cir c ui t
ad5233 rev. a | page 26 of 28 w o r k s un d e r s i n g le s u p p l y , th e p r ogra m m a b l e r e so l u ti o n o f th e sys t em is r e d u c e d . s e cond , t h e v o l t a g e com p li an ce a t v l is limi ted t o 2.5 v o r eq ui valen t l y a 125 ? lo ad . i f hig h er v o l t a g e co m p lian ce is neede d , us ers ca n co n s ider dig i t a l p o t e n t iom e t e rs ad5260, ad52 80, a n d ad7376 . f i gur e 58 s h o w s a n al ter n a t e cir c ui t f o r hig h v o l t a g e com p lian ce. t o achi e v e hig h er c u r r en t, s u ch as w h e n dr i v in g a hig h p o w e r led , t h e us er c a n r e plac e t h e u1 wi t h a n l d o , r e d u ce r s , a n d add a r e sis t o r in s e r i es wi t h the ad5233 s a t e r m inal . this l i mi ts t h e p o t e n t iom e ter s c u r r en t a n d enhan c es t h e c u r r en t a d ju st me n t re s o lut i on . pr ogr a mmable bidirec t ional current source f o r a p plica t ion s t h a t r e q u ir e b i dir e c t io na l c u r r en t con t r o l o r hig h er v o l t a g e c o m p li an ce, a h o w l and c u r r en t pum p can b e a so l u tio n (se e f i gur e 59). ? 15v op2177 v+ v? +15v + ? c1 10pf r2 15k ? r1 150k ? r2b 50 ? r l 500 ? v l r2a 14.95k ? r1 150k ? i l op2177 v+ v? +15v + ? ?15v a1 a d5233 a b w +2.5v ?2.5v a2 02794-a - 060 f i g u re 59. p r og r a m m ab le bid i rec t i o n a l cur r e n t s o urc e i f t h e r e sis t o r s ar e ma t c h e d , t h e lo ad c u r r en t is () + = ( 1 7 ) r2b , i n t h e o r y , ca n b e made as sma l l as ne cess ar y to achie v e t h e c u r r en t n e e d e d wi t h in t h e a2 ou t p u t c u r r en t-dr i v in g ca p a b i li ty . i n this cir c ui t, o p 2177 de li v e rs 5 ma in bo t h dir e c t ion s , and th e v o l t a g e com p lian ce a p p r o a ch es 15 v . w i t h ou t c1, i t ca n be shown t h a t t h e ou t p ut im p e danc e is o = ) ( ' ' ) ( ' r2b r2a r1 r1r2 r2a r1 r2b r1 + ? + (18) o ca n b e inf i nite, if r e sisto r s r1 and r2 ma tch p r e c is e l y wi t h r1 an d r2a + r2b , r e s p ecti v e l y . o n th e o t h e r h a n d , o ca n b e n e ga ti v e , i f th e r e s i s t o r s a r e n o t m a t c h e d . a s a r e s u l t , c1 in t h e ra n g e o f 1 f t o 10 pf i s n eeded t o p r ev e n t oscilla ti o n f r o m t h e ne g a t i v e i m p e d a nc e. resist ance sc aling ad5233 o f f e rs 10 k?, 50 k?, a n d 100 k? n o minal r e sis t an ce . u s er s wh o n e ed lo w e r r e sis t a n c e b u t wa n t t o ma in t a in t h e n u m b er o f ad j u s t m e n t s t eps c a n p a ral l e l m u l t i p le de vices. f o r exa m p l e , f i gur e 60 s h o w s a sim p le s c h e me o f p a ral l e l in g tw o ad5233 c h a n nels. t o ad j u s t half th e r e sis t an c e lin e a r l y p e r st ep , us ers n e e d t o p r og ra m bo t h de vices co n c ur r e n t ly wi t h t h e s a m e se t t in g s . a1 b1 w1 w2 a2 b2 ld v dd 02794-a - 061 f i gur e 6 0 . re duc e re si sta n c e b y hal f wi th li ne ar a d j u stme nt char act e r i sti c s i n v o l t a g e di vider m o de , b y pa ralle l in g a d i scr e te r e sis t o r a s sho w n i n f i g u re 6 1 , a prop or t i on a t ely l o we r vo l t age a p p e ar s a t t e r m ina l a t o b . this t r a n sl a t e s in t o a f i n e r deg r e e o f p r e c isio n, b e ca us e t h e s t ep size a t t e r m ina l w is smal ler . r2 r3 v dd r1 b w 0 a 02794-a - 062 f i gure 61. l o w e rin g the n o m i n a l r e s i s t anc e the v o l t a g e can b e fo und as fol l o w s: dd ab ab w v d r r r r r d v + = 64 // ) // ( ) ( 2 3 2 (19) f i gur e 60 a n d f i gur e 61 s h o w t h a t t h e dig i t a l p o t e n t iom e t e r ste p s ch ang e l i n e arly . o n t h e ot he r h a n d , l o g t a p e r a d j u st me n t i s u s u a l l y p r e f e r r e d i n ap p l i c at i o n s s u c h a s au d i o c o nt r o l . f i g u re 6 2 show s anot he r t y p e of re s i st anc e s c a l i n g . i n t h i s co nf igura t io n, t h e smal ler t h e r 2 wi t h r e s p e c t to r1, t h e m o r e t h e ps eudo log t a p e r cha r ac t e r i st ic o f t h e cir c ui t b e ha v e s. r1 r2 v o v i a b w 02794-a - 063 f i gur e 6 2 . resi st or sc ali n g wi th p s eud o l o g a d justm e nt cha r a c ter i stics
ad5233 rev. a | page 27 of 28 do ublin g the reso l u tio n rd a c circuit simul a tion model b o rr o w i n g f r o m a d i s p a t e n t e d r d a c se g m en ta ti o n t e c h n i q u e , t h e us er can conf igur e t h r e e cha nnels o f ad52 33, as sh own i n f i g u re 6 3 . by p a r a l l el i n g a d i s c re te re s i stor , r p ( r p = r ab /64), wi t h rd a c 3, the us er ca n dou b le th e r e s o l u tion o f ad5233 f r o m 6 b i ts t o 12 b i ts. one mig h t think tha t mo vin g rd a c 1 and r d a c 2 t o g e t h er w o ul d f o rm th e c o a r se 6 - b i t r e so l u ti o n , a n d th en m o v i n g rd a c 3 w o uld f o rm th e f i n e r 6-b i t r e so l u ti o n . a s a r e s u l t , t h e ef fe c t i v e r e s o l u t i o n wo u l d b e come 12 b i t s . h o w e v e r , t h e p r e c ision o f t h is cir c ui t r e ma in s o n ly 6- b i t a c c u ra t e and t h e p r ogra m m i n g ca n be c o m p l i ca t e d . the i n t e r n al p a rasi t i c c a p a ci t a nces a n d t h e ext e r n al lo ad do mina t e t h e ac c h a r ac t e r i s t ics o f t h e rd a c s. c o nf igur e d as a p o t e n t iom e t e r di vider , th e ?3 db ba ndwid t h o f th e ad5233 (10 k? r e sis t o r ) m e as ur es 370 kh z a t half-s cale . f i gur e 14 p r o v ides t h e la rg e sig n al b o d e plo t cha r ac t e r i s t ics. a p a rasi t i c sim u l a tio n mo de l is sh o w n in f i gur e 65. a rd a c 10k ? w c w 35pf c b 35pf c a 35pf 02749-a -066 b rdac1 a1 b1 v a w3 rdac3 a3 b3 rdac2 a2 b2 02794-a - 064 r p f i gure 65. r d a c ci rcuit s i m u l a ti on m o del f o r r d a c = 10 k t h e f o l l ow i n g c o d e prov i d e s a m a c r o - mo d e l n e t l i st f o r t h e 10 k? rd a c : listing i. spice model net list .param d = 64, rdac = 10e3 * .subckt dpot (a, w, b) * ca a 0 35e-12 rwa a w {(1-d/64)* rdac + 15} cw w 0 35-12 rwb w b {d/64 * rdac + 15} cb b 0 35e-12 * .ends dpot f i g u re 63. d o ub lin g a d 52 33 f r om 6 bi t s to 1 2 b i t s resist ance t o ler a nce, drift , and temper a t u r e misma t c h c o nsider a t ions i n a rh e o st a t mo de o p er a t io n suc h as ga in co n t r o l (s e e f i g u r e 64), th e t o le ra n c e m i s m a t c h be tw een th e d i gi tal po t e n t i - ome te r a n d t h e d i s c re te re s i stor c a n c a u s e re p e at abi l it y i ssu e s a m on g va r i o us sys t em s. b e c a us e o f t h e inher e n t ma t c hin g o f t h e silico n p r o c es s, i t is p r ac tic a l t o a p p l y the d u al- o r m u l t i p le- cha n n e l de vice i n t h is ty p e o f a pplica t ion. a s such, r1 can b e r e p l a c ed b y o n e o f th e c h a n n e ls o f th e d i g i tal p o t e n t i o m e t e r a n d p r ogra m m e d t o a s p ec if ic val u e . r2 ca n b e used f o r th e ad j u s t - able gain. a l t h oug h i t a dds co st, t h is a p p r o a ch mini mi zes t h e t o lera n c e an d te m p er a t ur e co ef f i cien t misma t ch b e tw e e n r1 a n d r2. t h is a p p r o a c h also trac ks the r e sis t an c e dr if t o v er tim e . a s a r e s u l t , al l no nideal p a ram e t e r s beco m e les s sen s i t i v e t o the sys t em va r i a t ion s . ad8601 + ? v i u1 v o c1 a b w r2 r1 * * replaced with another channel of rdac 02794-a - 065 f i gure 64. lin e ar g a in c o nt r o l w i th t r ack i ng resistance t o ler a nc e and t e mper ature coeffic i ent
ad5233 rev. a | page 28 of 28 outline dimensions 24 13 12 1 6.40 bsc 4.50 4.40 4.30 pin 1 7.90 7.80 7.70 0.15 0.05 0.30 0.19 0.65 bsc 1.20 max 0.20 0.09 0.75 0.60 0.45 8 0 seating plane 0.10 coplanarity compliant to jedec standards mo-153ad f i gure 66. 2 4 -l ead thin shr i nk s m a l l o u tline p a ckage [ t ssop ] (ru - 24) di me nsio ns sho w n i n mi ll im e t e r s ordering guide model no. of channels r ab (k ? ) temperature range package package option ordering quantity brand i ng 1 a d 5 2 3 3 b r u 1 0 4 1 0 ? 40c to +85c t s s o p - 2 4 r u - 2 4 9 6 5 2 3 3 b 1 0 AD5233BRU10- r e e l 7 4 1 0 ? 40c to +85c t s s o p - 2 4 r u - 2 4 1 , 0 0 0 5 2 3 3 b 1 0 ad5233bruz10 2 4 1 0 ? 40c to +85c t s s o p - 2 4 r u - 2 4 9 6 5 2 3 3 b 1 0 ad5233bruz10 -r7 2 4 1 0 ? 40c to +85c t s s o p - 2 4 r u - 2 4 1 , 0 0 0 5 2 3 3 b 1 0 a d 5 2 3 3 b r u 5 0 4 5 0 ? 40c to +85c t s s o p - 2 4 r u - 2 4 9 6 5 2 3 3 b 5 0 ad5233bru50- r e e l 7 4 5 0 ? 40c to +85c t s s o p - 2 4 r u - 2 4 1 , 0 0 0 5 2 3 3 b 5 0 ad5233bruz50 2 4 5 0 ? 40c to +85c t s s o p - 2 4 r u - 2 4 9 6 5 2 3 3 b 5 0 ad5233bruz50 -r7 2 4 5 0 ? 40c to +85c t s s o p - 2 4 r u - 2 4 1 , 0 0 0 5 2 3 3 b 5 0 AD5233BRU100 4 1 0 0 ? 40c to +85c t s s o p - 2 4 r u - 2 4 9 6 5 2 3 3 b 1 0 0 AD5233BRU100 - r e e l 7 4 1 0 0 ? 40c to +85c t s s o p - 2 4 r u - 2 4 1 , 0 0 0 5 2 3 3 b 1 0 0 ad5233bruz10 0 2 4 1 0 0 ? 40c to +85c t s s o p - 2 4 r u - 2 4 9 6 5 2 3 3 b 1 0 0 ad5233bruz10 0-r7 2 4 1 0 0 ? 40c to +85c t s s o p - 2 4 r u - 2 4 1 , 0 0 0 5 2 3 3 b 1 0 0 1 li n e 1 c o n t a i n s t h e m o d e l n u m b er . li n e 2 c o n t a i n s t h e ad i l o go f o llo w e d b y t h e en d- t o - e n d r e si s t a n c e v a lue . li n e 3 c o n t ai n s t h e da t e c o de , yww o r #y w w fo r pb -fre e par t s. 2 p b - f r ee par t . p u r c h a s e of li c e n s ed i2c c o m p on en t s of an a l og devi c e s or on e o f i t s sub l i c e n sed a s s oci a t e d c o m p a n i e s c o n v ey s a li c e n s e f o r t he pur c haser under the phi l ips i2 c p a t e n t r i gh t s t o us e t h e se c o m p on en t s i n a n i2 c sy st em , p r o v i d e d t h a t t h e sy s t em c o n f orm s t o t h e i2 c st a n da r d spec i f i c a t i o n a s defi n e d b y p h i l i p s . ? 2004 analo g de vices, inc. all rights reserve d . tra d em arks and registered tra d ema r ks are the prop erty of their respective owners . c02794C0 C 7/04(a)

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